Patents by Inventor Hidetoshi Kuraya
Hidetoshi Kuraya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11776884Abstract: A semiconductor device according to an embodiment includes a base frame, a semiconductor element provided on the base frame, a connector provided on the semiconductor element, the connector having an upper surface, a side surface, and a porous body having a plurality of pores provided on at least the side surface, and a molded resin provided in a periphery of the semiconductor element and at least the side surface of the connector. The upper surface of the connector is exposed.Type: GrantFiled: September 7, 2021Date of Patent: October 3, 2023Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Yuning Tsai, Hidetoshi Kuraya
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Patent number: 11735505Abstract: According to one embodiment, a semiconductor device includes a semiconductor chip, first and second conductive members, a first connection member, and a resin portion. The first conductive member includes first and second portions. The second portion is electrically connected to the semiconductor chip. A direction from the semiconductor chip toward the second portion is aligned with a first direction. A direction from the second portion toward the first portion is aligned with a second direction crossing the first direction. The second conductive member includes a third portion. The first connection member is provided between the first and third portion. The first connection member is conductive. The resin portion includes a first partial region. The first partial region is provided around the first and third portions, and the first connection member. The first portion has a first surface opposing the first connection member and including a recess and a protrusion.Type: GrantFiled: May 10, 2021Date of Patent: August 22, 2023Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Hidetoshi Kuraya, Satoshi Hattori, Kyo Tanabiki
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Publication number: 20220077029Abstract: A semiconductor device according to an embodiment includes a base frame, a semiconductor element provided on the base frame, a connector provided on the semiconductor element, the connector having an upper surface, a side surface, and a porous body having a plurality of pores provided on at least the side surface, and a molded resin provided in a periphery of the semiconductor element and at least the side surface of the connector. The upper surface of the connector is exposed.Type: ApplicationFiled: September 7, 2021Publication date: March 10, 2022Inventors: Yuning TSAI, Hidetoshi KURAYA
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Publication number: 20210265243Abstract: According to one embodiment, a semiconductor device includes a semiconductor chip, first and second conductive members, a first connection member, and a resin portion. The first conductive member includes first and second portions. The second portion is electrically connected to the semiconductor chip. A direction from the semiconductor chip toward the second portion is aligned with a first direction. A direction from the second portion toward the first portion is aligned with a second direction crossing the first direction. The second conductive member includes a third portion. The first connection member is provided between the first and third portion. The first connection member is conductive. The resin portion includes a first partial region. The first partial region is provided around the first and third portions, and the first connection member. The first portion has a first surface opposing the first connection member and including a recess and a protrusion.Type: ApplicationFiled: May 10, 2021Publication date: August 26, 2021Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Hidetoshi KURAYA, Satoshi HATTORI, Kyo TANABIKI
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Patent number: 11037863Abstract: According to one embodiment, a semiconductor device includes a semiconductor chip, first and second conductive members, a first connection member, and a resin portion. The first conductive member includes first and second portions. The second portion is electrically connected to the semiconductor chip. A direction from the semiconductor chip toward the second portion is aligned with a first direction. A direction from the second portion toward the first portion is aligned with a second direction crossing the first direction. The second conductive member includes a third portion. The first connection member is provided between the first and third portion. The first connection member is conductive. The resin portion includes a first partial region. The first partial region is provided around the first and third portions, and the first connection member. The first portion has a first surface opposing the first connection member and including a recess and a protrusion.Type: GrantFiled: March 7, 2018Date of Patent: June 15, 2021Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Hidetoshi Kuraya, Satoshi Hattori, Kyo Tanabiki
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Patent number: 10475949Abstract: An optical coupling device includes a first lead frame, a second lead frame, a first mounting member, a second mounting member, the members respectively provided on the first lead frame and, the second lead frame a light emitter provided on the first mounting member, a light receiver provided on the second mounting member, a first wire and a second wire electrically connecting the light emitter to the first lead frame, and the light receiver to the second lead frame, and an outer resin enclosure enclosing a part of the first lead frame and the second lead frame, the light emitter, and the light receiver, wherein at least the light emitter and the light receiver in the outer resin enclosure are covered with a silicone resin cured material.Type: GrantFiled: March 9, 2018Date of Patent: November 12, 2019Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventor: Hidetoshi Kuraya
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Publication number: 20190139866Abstract: According to one embodiment, a semiconductor device includes a semiconductor chip, first and second conductive members, a first connection member, and a resin portion. The first conductive member includes first and second portions. The second portion is electrically connected to the semiconductor chip. A direction from the semiconductor chip toward the second portion is aligned with a first direction. A direction from the second portion toward the first portion is aligned with a second direction crossing the first direction. The second conductive member includes a third portion. The first connection member is provided between the first and third portion. The first connection member is conductive. The resin portion includes a first partial region. The first partial region is provided around the first and third portions, and the first connection member. The first portion has a first surface opposing the first connection member and including a recess and a protrusion.Type: ApplicationFiled: March 7, 2018Publication date: May 9, 2019Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Hidetoshi KURAYA, Satoshi HATTORI, Kyo TANABIKI
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Publication number: 20190006551Abstract: An optical coupling device includes a first lead frame, a second lead frame, a first mounting member, a second mounting member, the members respectively provided on the first lead frame and, the second lead frame a light emitter provided on the first mounting member, a light receiver provided on the second mounting member, a first wire and a second wire electrically connecting the light emitter to the first lead frame, and the light receiver to the second lead frame, and an outer resin enclosure enclosing a part of the first lead frame and the second lead frame, the light emitter, and the light receiver, wherein at least the light emitter and the light receiver in the outer resin enclosure are covered with a silicone resin cured material.Type: ApplicationFiled: March 9, 2018Publication date: January 3, 2019Inventor: Hidetoshi Kuraya
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Patent number: 8597989Abstract: The yield of semiconductor devices is improved. In an upper die of a resin molding die including a pair of the upper die and a lower die, by lengthening the radius of the cross section of an inner peripheral surface of a second corner part facing an injection gate of a cavity more than that of the other corner part, a void contained in a resin in resin injection can be pushed out into an air vent without allowing the void to remain in the second corner part of the cavity. Consequently, the occurrence of the void in the cavity can be prevented and then the occurrence of the appearance defect of the semiconductor device can be prevented.Type: GrantFiled: December 24, 2012Date of Patent: December 3, 2013Assignee: Renesas Electronics CorporationInventors: Makio Okada, Hidetoshi Kuraya, Toshio Tanabe, Yoshinori Fujisaki, Kotaro Arita
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Patent number: 8349661Abstract: The yield of semiconductor devices is improved. In an upper die of a resin molding die including a pair of the upper die and a lower die, by lengthening the radius of the cross section of an inner peripheral surface of a second corner part facing an injection gate of a cavity more than that of the other corner part, a void contained in a resin in resin injection can be pushed out into an air vent without allowing the void to remain in the second corner part of the cavity. Consequently, the occurrence of the void in the cavity can be prevented and then the occurrence of the appearance defect of the semiconductor device can be prevented.Type: GrantFiled: January 12, 2012Date of Patent: January 8, 2013Assignee: Renesas Electronics CorporationInventors: Makio Okada, Hidetoshi Kuraya, Toshio Tanabe, Yoshinori Fujisaki, Kotaro Arita
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Publication number: 20120178220Abstract: The yield of semiconductor devices is improved. In an upper die of a resin molding die including a pair of the upper die and a lower die, by lengthening the radius of the cross section of an inner peripheral surface of a second corner part facing an injection gate of a cavity more than that of the other corner part, a void contained in a resin in resin injection can be pushed out into an air vent without allowing the void to remain in the second corner part of the cavity. Consequently, the occurrence of the void in the cavity can be prevented and then the occurrence of the appearance defect of the semiconductor device can be prevented.Type: ApplicationFiled: January 12, 2012Publication date: July 12, 2012Inventors: Makio Okada, Hidetoshi Kuraya, Toshio Tanabe, Yoshinori Fujisaki, Kotaro Arita
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Patent number: 7659635Abstract: A semiconductor device of the present invention includes a chip which has a pad; a bump electrode formed on the pad; and a wire whose stitch bonding is made on the bump electrode. The wire satisfies a condition: (modulus-of-elasticity/breaking strength per unit area)?400.Type: GrantFiled: September 4, 2008Date of Patent: February 9, 2010Assignee: Renesas Technology Corp.Inventors: Hidetoshi Kuraya, Hideyuki Arakawa, Fumiaki Aga
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Publication number: 20090001572Abstract: A semiconductor device of the present invention includes a chip which has a pad; a bump electrode formed on the pad; and a wire whose stitch bonding is made on the bump electrode. The wire satisfies a condition: (modulus-of-elasticity/breaking strength per unit area)?400.Type: ApplicationFiled: September 4, 2008Publication date: January 1, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Hidetoshi KURAYA, Hideyuki ARAKAWA, Fumiaki AGA
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Patent number: 7456091Abstract: A semiconductor device of the present invention includes a chip which has a pad; a bump electrode formed on the pad; and a wire whose stitch bonding is made on the bump electrode. The wire satisfies a condition: (modulus-of-elasticity/breaking strength per unit area) ?400.Type: GrantFiled: March 16, 2006Date of Patent: November 25, 2008Assignee: Renesas Technology Corp.Inventors: Hidetoshi Kuraya, Hideyuki Arakawa, Fumiaki Aga
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Publication number: 20060261495Abstract: A semiconductor device of the present invention includes a chip which has a pad; a bump electrode formed on the pad; and a wire whose stitch bonding is made on the bump electrode. The wire satisfies a condition: (modulus-of-elasticity/breaking strength per unit area) ?400.Type: ApplicationFiled: March 16, 2006Publication date: November 23, 2006Applicant: Renesas Technology Corp.Inventors: Hidetoshi Kuraya, Hideyuki Arakawa, Fumiaki Aga