Patents by Inventor Hidetoshi Naito

Hidetoshi Naito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8480990
    Abstract: A silica powder containing an ultrafine powder in an amount of from 0.1 to 20 mass % and having an average sphericity of at least 0.85, wherein the ultrafine powder has, as the particle size measured by a dynamic light scattering particle size distribution measuring apparatus, an average particle size of from 150 to 250 nm, less than 10 mass % of the ultrafine powder having a particle size of at most 100 nm being less than 10 mass % (not including 0 mass %) and from 10 to 50 mass % of the ultrafine powder having a particle size exceeding 100 nm and not exceeding 150 nm.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: July 9, 2013
    Assignee: Denki Kagaki Kogyo Kabushiki Kaisha
    Inventors: Syuji Sasaki, Hidetoshi Naito, Keishi Iizuka, Yasuhisa Nishi
  • Patent number: 8259766
    Abstract: A laser diode drive circuit includes: a duty control amplifier (23) that controls the duty ratio of a main signal for laser control in accordance with a duty control signal; and an AND gate (22) that outputs the duty control signal to the duty control amplifier (23), and outputs a duty control signal that controls the duty ratio of the main signal to be 0% in the duty control amplifier in accordance with a shutdown signal of a laser diode. With this structure, there is no need to input the main signal having the duty ratio controlled to a logic circuit that becomes unstable. Thus, outputs from a semiconductor laser can be shut down, and the output duty can be controlled in a stable manner.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: September 4, 2012
    Assignee: Eudyna Devices Inc.
    Inventor: Hidetoshi Naito
  • Publication number: 20100204383
    Abstract: To provide a silica powder which is excellent in flowability and packing properties and which is less likely to form a flash, a process for its production, and a composition having it incorporated in at least one of a rubber and a resin, particularly a sealing material. A silica powder containing an ultrafine powder in an amount of from 0.1 to 20 mass % and having an average sphericity of at least 0.85, wherein the ultrafine powder has, as the particle size measured by a dynamic light scattering particle size distribution measuring apparatus, an average particle size of from 150 to 250 nm, a content of particles having a particle size of at most 100 nm being less than 10 mass % (not including 0 mass %) and a content of particles having a particle size exceeding 100 nm and not exceeding 150 nm being from 10 to 50 mass %. A process for producing a silica powder, which comprises spraying a silica powder material to a high temperature zone of at least 1,750° C.
    Type: Application
    Filed: July 25, 2008
    Publication date: August 12, 2010
    Applicant: Denki Kagaku Kogyo Kabushiki Kaisha
    Inventors: Syuji Sasaki, Hidetoshi Naito, Keishi Iizuka, Yasuhisa Nishi
  • Publication number: 20090028200
    Abstract: A laser diode drive circuit includes: a duty control amplifier (23) that controls the duty ratio of a main signal for laser control in accordance with a duty control signal; and an AND gate (22) that outputs the duty control signal to the duty control amplifier (23), and outputs a duty control signal that controls the duty ratio of the main signal to be 0% in the duty control amplifier in accordance with a shutdown signal of a laser diode. With this structure, there is no need to input the main signal having the duty ratio controlled to a logic circuit that becomes unstable. Thus, outputs from a semiconductor laser can be shut down, and the output duty can be controlled in a stable manner.
    Type: Application
    Filed: September 30, 2008
    Publication date: January 29, 2009
    Applicant: EUDYNA DEVICES INC.
    Inventor: Hidetoshi NAITO
  • Patent number: 5994927
    Abstract: A circuit includes a middle-voltage-detection circuit which detects a substantially middle voltage between a HIGH level and a LOW level of a signal voltage, and supplies the substantially middle voltage as a reference voltage. The circuit further includes a differential amplifier which receives the signal voltage and the reference voltage.
    Type: Grant
    Filed: April 15, 1998
    Date of Patent: November 30, 1999
    Assignee: Fujitsu Limited
    Inventors: Hidetoshi Naito, Tatsuya Matsudo
  • Patent number: 5515386
    Abstract: A transmission circuit transmits a normal cell data and an idle cell data via a communication line. The idle cell data is transmitted to fill time slots in the communication line at which there is no normal data to be transmitted, each of the normal cell data and idle cell data including first data, second data and third data. The first, second and third data of the normal cell data respectively indicate a destination, an error correcting code of the first data and desired information. The first and second data of the idle cell data have predetermined bit patterns and the third data of the idle cell data may have any arbitrary bit pattern.
    Type: Grant
    Filed: September 23, 1994
    Date of Patent: May 7, 1996
    Assignee: Fujitsu Limited
    Inventors: Yuji Takizawa, Masaaki Kawai, Hidetoshi Naito, Kazuyuki Tajima, Satomi Ikeda
  • Patent number: 5408476
    Abstract: A 1-bit error correction circuit based on CRC calculation is provided with a syndrome generation circuit which determines input parallel data of m bits and which have been converted from n number of m-bit serial data. A 1-bit error detection circuit cyclically supplies a syndrome to a remainder calculation circuit and decodes remainder data obtained from this cyclic supply and detects 1-bit errors. A actual data reproduction circuit calculates the exclusive OR of output data of a predetermined register of a 1'st.about.n'th register of a syndrome generation circuit and data supplied to a predetermined register and obtains parallel data which is the actual data. A correction circuit which calculates a exclusive OR of parallel data obtained from a actual data reproduction circuit and 1-bit error data detected by the 1-bit error detection circuit and outputs corrected data.
    Type: Grant
    Filed: February 11, 1993
    Date of Patent: April 18, 1995
    Assignees: Fujitsu Limited, Nippon Telegraph and Telephone Corporation
    Inventors: Masaaki Kawai, Masayoshi Sekido, Yuji Takizawa, Hidetoshi Naito, Satomi Ikeda, Kazuyuki Tajima, Haruo Yamashita, Hideo Tatsuno
  • Patent number: 5265088
    Abstract: A cross-connection apparatus for B-ISDN includes plural interface units, multiplexers, virtual path identifier (VPI) conversion tables, demultiplexers, and loop-back units and a switch unit.
    Type: Grant
    Filed: June 2, 1992
    Date of Patent: November 23, 1993
    Assignees: Fujitsu Limited, Nippon Telegraph and Telephone Corporation
    Inventors: Yuji Takigawa, Masaaki Kawai, Hidetoshi Naito, Hisako Watanabe, Kazuyuki Tajima, Haruo Yamashita
  • Patent number: 5257311
    Abstract: A system for monitoring an ATM cross-connecting apparatus by inputting a test cell through a path for a main signal into the ATM cross-connecting apparatus, and examining the cell after the cell passed through the ATM cross-connecting apparatus. An initial value of a PN sequence and the PN sequence generated based on the initial bit sequence is written in the test cell before inputting to the ATM cross-connecting apparatus. When examining the test cell, the initial bit sequence and the PN sequence are read from the cell, a PN sequence is generated based on the initial bit sequence, and the generated pseudo-noise sequence is then compared with the PN sequence read from the test cell to detect an error in the test cell. In addition, a bit pattern indicating a primitive polynomial to generate the PN sequence may be written in the test cell. In this case, the bit pattern is used for generating the PN sequence when examining the test cell.
    Type: Grant
    Filed: April 30, 1992
    Date of Patent: October 26, 1993
    Assignee: Fujitsu Limited
    Inventors: Hidetoshi Naito, Masaaki Kawai, Hisako Watanabe, Yuji Takizawa, Kazuyuki Tajima, Haruo Yamashita