Abstract: The system effectively manipulates the operation of a charged particle flow device by approximating the total force on each ion during a trajectory calculation. The system applies the method in massively parallel general-purpose computing with GPU (GPGPU) to test its performance in simulations with thousands to over a million ions. The method calculates the forces on an ion using ions within an active region near the ion of interest. To decrease computation time, the method approximates the forces by calculating the ion-ion interactions within a first zone and the ion-ion cloud interactions within a second zone. The system adjusts settings of the charged particle flow device to affect the flow and positioning of the charged particles. Such setting may include adjusting the positioning of the charged plates, adjusting the voltage of the plates, and adjusting the pressure within the charged particle flow device.

Abstract: The invention is essentially a sequential (“DMA”) apparatus using a novel arrangement of at least three electrodes and at least two block electrodes to produce a DMA apparatus having at least two sequential DMA regions between pairs of adjacent electrode walls within the same housing. This apparatus is used to improve the transfer of particles into the subsequent DMA region without a vacuum or pump, and to improve the separation of target particles from non-target particles and concentration and collection of the target particles.

Abstract: The invention is essentially a sequential (“DMA”) apparatus using a novel arrangement of at least three electrodes and at least two block electrodes to produce a DMA apparatus having at least two sequential DMA regions between pairs of adjacent electrode walls within the same housing. This apparatus is used to improve the transfer of particles into the subsequent DMA region without a vacuum or pump, and to improve the separation of target particles from non-target particles and concentration and collection of the target particles.

Abstract: Jitterless transition of the programmable clock waveform is generated employing a set of two coupled direct digital synthesis (DDS) circuits. The first phase accumulator in the first DDS circuit runs at least one cycle of a common reference clock for the DDS circuits ahead of the second phase accumulator in the second DDS circuit. As a phase transition through the beginning of a phase cycle is detected from the first phase accumulator, a first phase offset word and a second phase offset word for the first and second phase accumulators are calculated and loaded into the first and second DDS circuits. The programmable clock waveform is employed as a clock input for the RAM address controller. A well defined jitterless transition in frequency of the arbitrary waveform is provided which coincides with the beginning of the phase cycle of the DDS output signal from the second DDS circuit.

Abstract: Jitterless transition of the programmable clock waveform is generated employing a set of two coupled direct digital synthesis (DDS) circuits. The first phase accumulator in the first DDS circuit runs at least one cycle of a common reference clock for the DDS circuits ahead of the second phase accumulator in the second DDS circuit. As a phase transition through the beginning of a phase cycle is detected from the first phase accumulator, a first phase offset word and a second phase offset word for the first and second phase accumulators are calculated and loaded into the first and second DDS circuits. The programmable clock waveform is employed as a clock input for the RAM address controller. A well defined jitterless transition in frequency of the arbitrary waveform is provided which coincides with the beginning of the phase cycle of the DDS output signal from the second DDS circuit.