Patents by Inventor Hideyuki Arakawa
Hideyuki Arakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240171730Abstract: A video decoding device, in the case where a video of the progressive format is inputted, processes a frame as a picture, in the case where a video of the interlace format is inputted, processes a field as a picture. A video decoding device performs display control corresponding to a format of the both video by analyzing display control information in display control information analyzer. The display control information includes sequence unit display control information which is commonly used in a display process of all pictures that belong to a sequence to be decoded and picture unit display control information which is individually used in a display process of a picture to be decoded. A second code string analyzer acquires each of the sequence unit display control information and the picture unit display control information from an extended information area in units of pictures.Type: ApplicationFiled: December 27, 2023Publication date: May 23, 2024Inventors: Kiyofumi ABE, Kazuhito KIMURA, Hideyuki OHGOSE, Hiroshi ARAKAWA, Koji ARIMURA
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Patent number: 9230937Abstract: There is provided a technology capable of suppressing the damage applied to a pad. When the divergence angle of an inner chamfer part is smaller than 90 degrees, the ultrasonic conversion load in a direction perpendicular to the surface of the pad is very small in magnitude. In other words, the ultrasonic conversion load in a direction perpendicular to the surface of the pad is sufficiently smaller in magnitude than the ultrasonic conversion load in a direction in parallel with the surface of the pad. Consequently, when the divergence angle of the inner chamfer part is smaller than 90 degrees, the ultrasonic conversion load in a direction perpendicular to the surface of the pad can be sufficiently reduced in magnitude, which can prevent pad peeling.Type: GrantFiled: May 10, 2012Date of Patent: January 5, 2016Assignee: Renesas Electronics CorporationInventors: Kaori Sumitomo, Hideyuki Arakawa, Hiroshi Horibe, Yasuki Takata
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Patent number: 8881966Abstract: An improvement in the quality of wire bonding is achieved by reducing the vibration of a lead frame or a wiring substrate after wire bonding. Over a heat block in a wire bond portion of a wire bonder, there is provided a cooling blower for cooling a wire-bonded matrix frame so that the temperature thereof may decrease stepwise. After wire bonding, cold air is blown from the cooling blower to the matrix frame, and temperature control of the matrix frame is performed so that the temperature of the matrix frame after wire bonding may decrease stepwise. Or, the wire-bonded matrix frame is fixed with a holding tool such as a frame holding member, a guide member, a roller means, or an elastic means until cooling is completed.Type: GrantFiled: December 9, 2009Date of Patent: November 11, 2014Assignee: Renesas Electronics CorporationInventors: Kazuyuki Misumi, Hideyuki Arakawa, Shunji Yamauchi, Mitsuru Aoki
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Patent number: 8415245Abstract: Height control of a capillary is performed in a stitch bonding (2nd bond) in a wire bonding, so that a thickness of a stitch portion can be controlled, thereby ensuring a bonding strength at the stitch portion and achieving an improvement in a bonding reliability. Also, the stitch portion has a thick portion, and a wire and a part (? portion) of a bonding region of an inner lead is formed to a lower portion of the thick portion, thereby sufficiently ensuring a thickness of the stitch portion and a bonding region.Type: GrantFiled: September 9, 2010Date of Patent: April 9, 2013Assignee: Renesas Electronics CorporationInventors: Yasuki Takata, Kaori Sumitomo, Hiroshi Horibe, Hideyuki Arakawa
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Publication number: 20120286427Abstract: There is provided a technology capable of suppressing the damage applied to a pad. When the divergence angle of an inner chamfer part is smaller than 90 degrees, the ultrasonic conversion load in a direction perpendicular to the surface of the pad is very small in magnitude. In other words, the ultrasonic conversion load in a direction perpendicular to the surface of the pad is sufficiently smaller in magnitude than the ultrasonic conversion load in a direction in parallel with the surface of the pad. Consequently, when the divergence angle of the inner chamfer part is smaller than 90 degrees, the ultrasonic conversion load in a direction perpendicular to the surface of the pad can be sufficiently reduced in magnitude, which can prevent pad peeling.Type: ApplicationFiled: May 10, 2012Publication date: November 15, 2012Inventors: Kaori Sumitomo, Hideyuki Arakawa, Hiroshi Horibe, Yasuki Takata
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Patent number: 7943433Abstract: A semiconductor chip has a rectangular main surface with first and second vertices on a diagonal line and first and second sides connecting the first and second vertices. A wire is formed between an electrode and a pad of the semiconductor chip. The wire is enclosed in a cavity of a mold. A liquid resin is poured into the cavity to flow from the first vertex toward the second vertex along the first and second sides. The liquid resin is cured to form a resin portion. The wire is formed such that the wire extends on the side relatively further from the first vertex with respect to a straight line connecting the pad and electrode as seen in plan view. Wires are thus prevented from contacting each other in the process of pouring the liquid resin and accordingly electrical short circuit between the wires can be prevented.Type: GrantFiled: October 29, 2009Date of Patent: May 17, 2011Assignee: Renesas Electronics CorporationInventor: Hideyuki Arakawa
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Publication number: 20110057299Abstract: Height control of a capillary is performed in a stitch bonding (2nd bond) in a wire bonding, so that a thickness of a stitch portion can be controlled, thereby ensuring a bonding strength at the stitch portion and achieving an improvement in a bonding reliability. Also, the stitch portion has a thick portion, and a wire and a part (? portion) of a bonding region of an inner lead is formed to a lower portion of the thick portion, thereby sufficiently ensuring a thickness of the stitch portion and a bonding region.Type: ApplicationFiled: September 9, 2010Publication date: March 10, 2011Inventors: Yasuki TAKATA, Kaori Sumitomo, Hiroshi Horibe, Hideyuki Arakawa
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Publication number: 20100203681Abstract: An improvement in the quality of wire bonding is achieved by reducing the vibration of a lead frame or a wiring substrate after wire bonding. Over a heat block in a wire bond portion of a wire bonder, there is provided a cooling blower for cooling a wire-bonded matrix frame so that the temperature thereof may decrease stepwise. After wire bonding, cold air is blown from the cooling blower to the matrix frame, and temperature control of the matrix frame is performed so that the temperature of the matrix frame after wire bonding may decrease stepwise. Or, the wire-bonded matrix frame is fixed with a holding tool such as a frame holding member, a guide member, a roller means, or an elastic means until cooling is completed.Type: ApplicationFiled: December 9, 2009Publication date: August 12, 2010Inventors: KAZUYUKI MISUMI, Hideyuki Arakawa, Shunji Yamauchi, Mitsuru Aoki
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Patent number: 7763966Abstract: A plurality of inner leads 14 are provided around a die pad 13. A grounded GND lead 16 is provided in a region between the die pad 13 and the plurality of inner leads 14. A semiconductor chip 17 and the plurality of inner leads 14 are connected to each other by a plurality of wires 21. The semiconductor chip 17 and the GND lead 16 are connected to each other by GND wires 22. The GND wires 22 are disposed between a plurality of wires 21. The distance between ends of each adjacent pair of the inner leads 14 is 0.2 mm or less.Type: GrantFiled: March 5, 2008Date of Patent: July 27, 2010Assignee: Renesas Technology Corp.Inventors: Kazuyuki Misumi, Kazushi Hatauchi, Yasuki Takata, Naoya Yasuda, Hideyuki Arakawa, Katsuyuki Fukudome
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Publication number: 20100120207Abstract: A semiconductor chip has a rectangular main surface with first and second vertices on a diagonal line and first and second sides connecting the first and second vertices. A wire is formed between an electrode and a pad of the semiconductor chip. The wire is enclosed in a cavity of a mold. A liquid resin is poured into the cavity to flow from the first vertex toward the second vertex along the first and second sides. The liquid resin is cured to form a resin portion. The wire is formed such that the wire extends on the side relatively further from the first vertex with respect to a straight line connecting the pad and electrode as seen in plan view. Wires are thus prevented from contacting each other in the process of pouring the liquid resin and accordingly electrical short circuit between the wires can be prevented.Type: ApplicationFiled: October 29, 2009Publication date: May 13, 2010Inventor: Hideyuki ARAKAWA
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Patent number: 7659635Abstract: A semiconductor device of the present invention includes a chip which has a pad; a bump electrode formed on the pad; and a wire whose stitch bonding is made on the bump electrode. The wire satisfies a condition: (modulus-of-elasticity/breaking strength per unit area)?400.Type: GrantFiled: September 4, 2008Date of Patent: February 9, 2010Assignee: Renesas Technology Corp.Inventors: Hidetoshi Kuraya, Hideyuki Arakawa, Fumiaki Aga
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Patent number: 7622799Abstract: A semiconductor device in which memory chips are stacked on the surface of a wiring substrate has a microcomputer chip and an interposer chip arranged on the surface of the memory chip. The pads of the microcomputer chip and the pads of the interposer chip are arranged almost circularly and are connected by bonding wires.Type: GrantFiled: December 28, 2006Date of Patent: November 24, 2009Assignee: Renesas Technology Corp.Inventors: Soshi Kuroda, Naoya Yasuda, Hideyuki Arakawa, Akira Yamazaki, Koji Bando
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Publication number: 20090001572Abstract: A semiconductor device of the present invention includes a chip which has a pad; a bump electrode formed on the pad; and a wire whose stitch bonding is made on the bump electrode. The wire satisfies a condition: (modulus-of-elasticity/breaking strength per unit area)?400.Type: ApplicationFiled: September 4, 2008Publication date: January 1, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Hidetoshi KURAYA, Hideyuki ARAKAWA, Fumiaki AGA
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Patent number: 7456091Abstract: A semiconductor device of the present invention includes a chip which has a pad; a bump electrode formed on the pad; and a wire whose stitch bonding is made on the bump electrode. The wire satisfies a condition: (modulus-of-elasticity/breaking strength per unit area) ?400.Type: GrantFiled: March 16, 2006Date of Patent: November 25, 2008Assignee: Renesas Technology Corp.Inventors: Hidetoshi Kuraya, Hideyuki Arakawa, Fumiaki Aga
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Publication number: 20080217750Abstract: A plurality of inner leads 14 are provided around a die pad 13. A grounded GND lead 16 is provided in a region between the die pad 13 and the plurality of inner leads 14. A semiconductor chip 17 and the plurality of inner leads 14 are connected to each other by a plurality of wires 21. The semiconductor chip 17 and the GND lead 16 are connected to each other by GND wires 22. The GND wires 22 are disposed between a plurality of wires 21. The distance between ends of each adjacent pair of the inner leads 14 is 0.2 mm or less.Type: ApplicationFiled: March 5, 2008Publication date: September 11, 2008Inventors: Kazuyuki Misumi, Kazushi Hatauchi, Yasuki Takata, Naoya Yasuda, Hideyuki Arakawa, Katsuyuki Fukudome
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Publication number: 20080054052Abstract: A manufacturing method of a semiconductor device which can cut a wire easily, can obtain a suitable-shaped bump electrode, and can pull out a wire easily from a capillary is obtained. The method includes the step of forming a bump electrode on a pad with the wire which passed to the capillary after the portion has eaten away in a capillary, a step at which a capillary is raised only 30 ?m˜45 ?m, a step which dwindles the wire which makes a capillary move only 35 ?m˜55 ?m to a horizontal direction after raising a capillary, a step which pulls out a wire from the capillary which raises a capillary after dwindling a wire, and the step which cuts a wire by pulling upward on both sides of a wire by a clamper after pulling out a wire from a capillary.Type: ApplicationFiled: August 3, 2007Publication date: March 6, 2008Inventor: Hideyuki ARAKAWA
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Publication number: 20070170573Abstract: The semiconductor device with which bonding wires cannot contact easily is offered. In this semiconductor device, memory chips are stacked on the surface of a wiring substrate, a microcomputer chip and an interposer chip are arranged on the surface of the memory chip, and the pad of a microcomputer chip and the pad of an interposer chip arranged almost circularly are connected by a bonding wire. Therefore, since the transfer pressure of liquid resin for sealing can be weakened with a wire, contact of the wires by deformation of a wire can be prevented.Type: ApplicationFiled: December 28, 2006Publication date: July 26, 2007Inventors: Soshi KURODA, Naoya Yasuda, Hideyuki Arakawa, Akira Yamazaki, Koji Bando
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Publication number: 20060261495Abstract: A semiconductor device of the present invention includes a chip which has a pad; a bump electrode formed on the pad; and a wire whose stitch bonding is made on the bump electrode. The wire satisfies a condition: (modulus-of-elasticity/breaking strength per unit area) ?400.Type: ApplicationFiled: March 16, 2006Publication date: November 23, 2006Applicant: Renesas Technology Corp.Inventors: Hidetoshi Kuraya, Hideyuki Arakawa, Fumiaki Aga
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Publication number: 20060216863Abstract: A method of manufacturing a semiconductor device includes a step of preparing a first chip having a plurality of first pads and a second chip having a plurality of second pads, a step of forming a first bump electrode on one of the plurality of first pads by a wire fed out from a capillary, a step of forming a first wire electrically connecting one of the first bump electrode and one of the plurality of second pads by the wire fed out from the capillary after the step of forming the first bump electrode, and a step of forming a second bump electrode on another of the plurality of first pads by the wire fed out from the capillary after the step of forming the first wire.Type: ApplicationFiled: February 6, 2006Publication date: September 28, 2006Applicant: Renesas Technology Corp.Inventor: Hideyuki Arakawa
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Patent number: 6774494Abstract: A semiconductor device includes an inner lead, a first ball on the inner lead, a bonding pad on the semiconductor device, a second ball on the bonding pad, and a bonding wire connecting the first and second balls. The second ball is formed by mechanically deforming the bonding wire.Type: GrantFiled: August 23, 2001Date of Patent: August 10, 2004Assignee: Renesas Technology Corp.Inventor: Hideyuki Arakawa