Abstract: Disclosed is a card connector comprising a double-deck shell assembly having upper and lower shell compartments for accommodating memory devices in the form of cards, and a pin connector assembly having connection pins adapted to be received in receptacles of each memory device inserted in the associated shell compartment. The pin connector assembly is adapted to be soldered directly to a printed circuit board, and the shell assembly is adapted to be assembled to the connector assembly thus fixed on the printed circuit board. Also disclosed is an assembly method for such a card connector.

Abstract: Disclosed is an improved card connector comprising a shell assembly and a pin connector assembly. The pin connector assembly includes an insulating housing mounting upper and lower rows of signal terminals and an upper and lower grounding terminal. The signal terminals include connection pins arranged in upper and lower rows and solder tails for connecting to an underlying printed circuit board. The upper grounding terminal includes a downwardly extending rear wall having window apertures formed therein. The upper rows of signal pins pass through the window apertures without contacting the grounding terminal and terminate at the solder tails. The upper and lower grounding terminals are electrically coupled, and a single row of DIP-type solder tails extending from the lower grounding terminals can be soldered to selected conductors on a printed circuit board to couple both of the grounding terminals to a ground circuit of the printed circuit board.

Abstract: Disclosed is an improved card connector comprising a shell assembly and a pin connector assembly. The pin connector assembly includes an insulating housing having a plurality of signal terminals and grounding terminals mounted therein. Connection pins of the signal terminals are arranged in upper and lower rows in the insulating housing. The grounding terminals are arranged parallel to the connection pins at upper and lower levels. The upper and lower grounding terminals are electrically coupled by way of coupling contacts, and a single row of DIP-type solder tails extending from the lower grounding terminals can be soldered to selected conductors on a printed circuit board to couple both grounding terminals to the ground circuit of the circuit board.

Abstract: An electrical connector with enhanced grounding characteristics which reduce the possibility of signal transmission error includes a connector housing formed from an electrically insulative material, a plurality of conductive terminals mounted on the connector housing, the terminals having tail portions which extend out of and away from the connector housing for attachment to a printed circuit board. A conductive grounding plate, in the form of a metal shield, is mounted to the exterior of the connector housing The grounding plate incudes at least one grounding terminal integrally formed therewith at extending outwardly therefrom at the level of the connector conductive terminals in a space between two adjoining conductive terminals.

Abstract: An improved electrical connector assembly for mounting to a printed circuit board (6) and for receiving a PC card. The electrical connector assembly includes a housing (3) having signal terminals (1) and ground terminals (2), wherein the tail portions (11) of the signal terminals are of surface mount type and the tail portions (21) of the ground terminals are of through-hole type. The tail portions of the ground terminals extend in at least one row toward the circuit board between the tail portions of the signal terminals and the rear end of the housing. In this configuration, the signal terminal tail portions and the ground terminal tail portions can be simultaneously soldered and all of the solder joints can be inspected without obstruction, the surface mount solder joints inspected from an upper surface (7) of the circuit board and the through-hole solder joints can be inspected from a lower surface (8) of the circuit board.

Abstract: Disclosed is an improved method of forming a two-storied type of PC card connector assembly. It comprises the steps of: attaching one card connector to one side of a printed circuit board; soldering the soldering tails of the signal terminals to the signal circuit pattern formed on the one side of the printed circuit board, and the soldering tails of the ground terminals to the through-holes made in the printed circuit board; attaching the other card connector to the other side of the printed circuit board (no ground terminal piece attached thereto); soldering the soldering tails of the signal terminals to the circuit pattern formed on the other side of the printed circuit board; press-fitting a separate ground terminal piece in the other card connector; and soldering the soldering tails of the ground terminal piece to the ground circuit pattern formed on the other side of the printed circuit board.

Abstract: An IC card connector apparatus including a lock mechanism comprising: a box-type casing having card-receiving opening formed at one end thereof for inserting and ejecting an IC card; an electric connector mounted within said casing opposite said opening for mating with an edge of the IC card; and an eject mechanism including an eject rod disposed on one side of the casing. The connector apparatus further includes a shutter plate slidably mounted at one end of said insertion opening for preventing passage of the IC card therethrough when in a blocking position; and an ON-OFF switch operatively associated with said shutter plate to shut off the electrical connection between the IC card and the connector when the shutter plate is in an open position. One end of said shutter plate engages an end portion of said eject rod as a result of the slide movement of said shutter plate into its blocking position.

Abstract: An eject mechanism for a card-receiving connector equipped with a foldable eject button which provides sufficient mechanical ejection stroke without excess projection of the ejection button from a front face of an electronic apparatus. The card ejection mechanism includes an eject rod, an eject button connected to the ejection rod, and an actuation lever for ejecting a memory card from the card-receiving connector. The eject button includes a base button and an operation button. The operation button is pivotally connected to the base button and is mounted for movement between a raised position where the operation button is axially aligned with base button, and a folded position where the operation button is oriented generally perpendicular to the base button. The operation button includes a base portion for engaging a corresponding recess in the base button for holding the operation button in its raised position.

Abstract: An improved connector terminal has a profile which facilitates insertion into engagement holes on a circuit board and increases resistance to deformation. The terminals may be part of an assembly which includes a series of terminals arranged in a spaced-apart array. Each has a solder tail portion defined by a straight edge (11) proximate to the centerline (9) and a slanted edge (12) which diagonally extends from the other side and which traverses the centerline (9) to intersect with the straight edge (11) to thereby form an acute angle at the tip (E) of the terminal near the centerline (9) to provide comparable positioning allowances on the opposite sides of the centerline (9) to facilitate mounting of the terminals on a circuit board. The acute angle point is advantageous to the optical measurement of terminal intervals for the quality control.

Abstract: In an elastic store supplied with a sequence of reception data, a sequence of reception clock pulses, a sequence of reception frame pulses, a sequence of system clock pulses, and a sequence of system frame pulses comprising successive system frames each of which has a system frame phase, a first signal generating circuit alternately controls write-in operation of first and second data memory blocks in response to the reception clock pulses and the reception frame pulses. The first and the second data memory blocks thereby memorize the reception data as first and second memorized data, respectively. A second signal generating circuit alternately controls read-out operation of the first and the second data memory blocks in response to the system clock pulses and the system frame pulses. The first and the second data memory blocks thereby deliver the first and the second memorized data as first and second read-out data, respectively.

Abstract: An edge connector is adapted for use with a printed circuit board having a mating edge and a plurality of contact pads on opposite sides of the board adjacent the edge. The connector includes an elongated dielectric housing having a slot for receiving the mating edge of the printed circuit board. A plurality of terminals are mounted on the housing along the slot. Each terminal includes a pair of side support portions fixed to the housing outside opposite sides of the slot, a cross brace portion extending between the side support portions, a terminating portion projecting below the cross brace portion and a spring contact arm projecting upwardly from the cross brace portion and including a contact portion for engaging one of the contact pads on the printed circuit board. The terminals are oriented in an alternating array along the slot whereby the contact portions alternatingly engage contact pads on opposite sides of the printed circuit board.

Abstract: An edge connector is adapted for use with a printed circuit board having a mating edge and a plurality of contact pads on opposite sides of the board adjacent the edge. The connector includes an elongated dielectric housing having a slot for receiving the mating edge of the printed circuit board. A plurality of terminals are mounted on the housing along the slot. Each terminal includes a pair of side support portions fixed to the housing generally near opposite sides of the slot, a cross brace portion extending between the side support portions, a terminating portion projecting below the cross brace portion and a spring contact portion projecting above the cross brace portion for engaging one of the contact pads on the printed circuit board. The spring contact portion extends from one side of the terminal across the slot for engaging a contact pad on an opposite side of the printed circuit board.

Abstract: An ISDN response system comprises a plurality of terminals, each of which contains a SETUP message to an incoming all. Each terminal has the same subscriber number with the same attribute values and responds to a first SETUP message received by it which has the aforementioned subscriber number and attribute values to transmit a CONN message to the termination so that communication is established between the network and the particular terminal, the CONN message of which is first received at the termination. The timing of the transmission of the CONN message sent by the particular terminal is delayed when a subsequent SETUP message is received having the same subscriber number and attribute values.

Abstract: The disclosed data switching apparatus comprises an input control unit which separates a header from communication data contained in logical channel data, as associative memory which compares the header with incoming logical channel numbers previously registered and which outputs an address control signal associated with an address where any of the incoming logical channel numbers coincident with the header are stored, a temporary storage circuit for outputting, based on the address control circuit, an outgoing logical channel number previously registered and associated with the coincident incoming logical channel number, a communication data buffer for temporarily storing the communication data, and an ouput control unit for combining the outgoing logical channel number from the temporary circuit and the communication data from the communication data buffer and delivering the combination to the outgoing communication channel.

Abstract: A time switch with a dual structure-type control memory utilizing a time division time switch. The switch is equipped with a speech memory unit into which digital signals to be interchanged are temporarily written, and a control memory unit into which addresses to be accessed by the speech memory unit are written. The control memory unit has first and second memories. Each memory has an input/output section connected to a memory controller. The memories are set during hard and soft cycles so that when either one of the memories is set in a hard cycle the other memory is set in a soft cycle. The hard cycle is a speech-control data read-only mode. The soft cycle is a speech-control data read-write mode under control from the memory controller.

Abstract: A packet switching system mainly consists of a packet transmission controller, connected to a line group, for performing transmission control of a data packet, and a packet switching unit for receiving the data packet from the packet transmission controller to perform switching processing. The packet switching unit includes a packet separator for separating the data packet into a header part and a data part, a packet header processor for updating the separated header part, a packet data buffer for storing the separated data part, and a packet combiner for combining the output from the packet data buffer and the output from the packet header processor and supplying a combined packet to the packet transmission controller.

Abstract: A subscriber line interface circuit described wherein a pair of line terminals are connected to a subscriber loop and a pair of output terminals are connected to a telecommunication exchange. A first amplifier is provided having a first pair of input terminals coupled to the line terminals and a second pair of input terminals. The first amplifier has a unity gain over a path from the input terminals of the first pair to said output terminals and a gain K over a path from the terminals of the second pair to said output terminals. A pair of reference resistors are cross-coupled from said output terminals to the line terminals, each of the reference resistors having a resistance Ro. A second amplifier is connected from the line terminals to the terminals of the second pair, the second amplifier having a transfer function -Ro/K.multidot.Zt, where Zt is an impedance to be synthesized across the line terminals.