Patents by Inventor Hieu T. Tran

Hieu T. Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120052126
    Abstract: Nanoemulsions contain particles that comprise an outer shell layer containing at least one oil and a core portion containing at least one antioxidant and, optionally, other health-promoting compounds, wherein the nanoemulsions are relatively stable for prolonged periods without significant change in physical properties and are suitable for administering to humans and other mammals orally, topically, intravenously, transdermally, and subcutaneously.
    Type: Application
    Filed: August 29, 2011
    Publication date: March 1, 2012
    Inventors: Yashwant Pathak, Hieu T. Tran
  • Patent number: 7764709
    Abstract: A plurality of packets associated with a plurality of protocols are received, wherein the plurality of packets are to be processed by a plurality of processors. Packets associated with a first protocol are sent to be processed by at least one of the plurality of processors before sending packets associated with a second protocol to be processed, in response to determining that the packets associated with the first protocol have a higher priority for processing than the packets associated with the first protocol.
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: July 27, 2010
    Inventors: Hieu T. Tran, Dinesh Kumar, Kiran A. Patil, Linden Cornett
  • Patent number: 7065598
    Abstract: Provided are a method, system and article of manufacture for adjusting interrupt levels. A current system interrupt rate at a computational device is determined, wherein the current system interrupt rate is a sum of interrupt rates from a plurality of interrupt generating agents. The current system interrupt rate is compared with at least one threshold interrupt rate associated with the computational device. Based on the comparison, an interrupt moderation level is adjusted at an interrupt generating agent of the plurality of interrupt generating agents.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: June 20, 2006
    Assignee: Intel Corporation
    Inventors: Patrick L. Connor, Eric K. Mann, Hieu T. Tran, Priya Govindarajan, John P. Jacobs, David M. Durham, Gary D. Gumanow, Chun Yang Chiu
  • Publication number: 20040249933
    Abstract: In general, in one aspect, the disclosure describes a method that includes automatically applying different sets of parameter values to a network interface component, storing performance data for the network interface component for the different sets of parameter values, and selecting a one of the different sets of parameters values based on the performance data.
    Type: Application
    Filed: June 4, 2003
    Publication date: December 9, 2004
    Inventors: Priva Govindarajan, Patrick L. Connor, Eric K. Mann, Hieu T. Tran, John P. Jacobs, David M. Durham, Gary D. Gumanow, Chun Yang Chiu, Wayne J. Swick
  • Publication number: 20040123008
    Abstract: Provided are a method, system and article of manufacture for adjusting interrupt levels. A current system interrupt rate at a computational device is determined, wherein the current system interrupt rate is a sum of interrupt rates from a plurality of interrupt generating agents. The current system interrupt rate is compared with at least one threshold interrupt rate associated with the computational device. Based on the comparison, an interrupt moderation level is adjusted at an interrupt generating agent of the plurality of interrupt generating agents.
    Type: Application
    Filed: December 20, 2002
    Publication date: June 24, 2004
    Applicant: Intel Corporation
    Inventors: Patrick L. Connor, Eric K. Mann, Hieu T. Tran, Priya Govindarajan, John P. Jacobs, David M. Durham, Gary D. Gumanow, Chun Yang Chiu
  • Patent number: 6438686
    Abstract: A method and apparatus for eliminating contention with dual masters. One method disclosed disables a default bus master, and tests for a second bus master. If the second bus master fails to respond, the default bus master is enabled.
    Type: Grant
    Filed: April 20, 1999
    Date of Patent: August 20, 2002
    Assignee: Intel Corporation
    Inventors: Gregory M. Daughtry, Hieu T. Tran, Srithar Ramesh, Andrew J. McRonald