Abstract: A semiconductor memory device which has a reduced current consumption. A memory block includes a pair of memory cell columns each of which includes a plurality of memory cells connected in series, the memory cell columns being connected in series in a column direction along which the memory cells are arranged, a position of each of the memory cells being indicated by address data comprising first address data and second address data. Each of a plurality of word lines is connected to a corresponding one of the memory cells included in the memory block on a one to one basis. A memory cell column selection decoder selects one of the memory cell columns based on the first address data. A word line selection decoder selects one of the word lines based on the second address data and a control signal which is logically equivalent to the first address data. Additional memory blocks may be arranged in a row direction perpendicular to the column direction.

Abstract: A state control portion causes a sense amplifier portion to be at an active state and for causing the sense amplifier to be at an inactive state. A feedback portion causes the control device to causing the sense amplifier portion to be in the inactive state when a path is formed between a power source and a ground in the sense amplifier. A latch portion holds an output of the sense amplifier output when the path is formed. The state control portion comprises a first transistor acting as a switching device. The feedback portion produces a control signal using an output of the sense amplifier portion and a clock signal obtained from a detection circuit, and supplies the control signal to the first transistor. A second transistor for precharging is connected between the first transistor and the power source.

Abstract: A state control portion causes a sense amplifier portion to be at an active state and for causing the sense amplifier to be at an inactive state. A feedback portion causes the control device to causing the sense amplifier portion to be in the inactive state when a path is formed between a power source and a ground in the sense amplifier. A latch portion holds an output of the sense amplifier output when the path is formed. The state control portion comprises a first transistor acting as a switching device. The feedback portion produces a control signal using an output of the sense amplifier portion and a clock signal obtained from a detection circuit, and supplies the control signal to the first transistor. A second transistor for precharging is connected between the first transistor and the power source.

Abstract: A semiconductor memory device having a small chip area is provided to reduce a manufacturing cost. The semiconductor memory device has memory unit comprising memory cells arranged in a matrix comprising n rows and m columns, where m.gtoreq.2 and n.gtoreq.1, each of the memory cells having a single port and being capable of storing a single word of data comprising at least one bit, the memory cells arranged in a single column forming a memory cell block. The semiconductor memory device selects one set of two memory cells, one from an arbitrary memory cell block and the other from a different memory cell block. A reading operation performed and a writing operation for the set of two memory cells are performed during the same cycle.

Abstract: A memory apparatus includes a memory cell array in which a plurality of memory cells are arranged in a matrix formation and divided into blocks, a writing part for serially writing data to the memory cell array through a set of writing bit lines, each of the writing bit lines connected to one of the blocks, a reading part for serially reading the data from the memory cells of the memory cell array through a set of reading bit lines, each of the reading bit lines connected to one of the blocks, and a set of precharging units each for presetting one of the reading bit lines to a prescribed voltage when data is read from one of the blocks of the memory cell array.

Abstract: A semiconductor integrated circuit apparatus has a basic cell region formed by arranging a plurality of basic cells each including a MOS transistor in longitudinal and transversal directions. The MOS transistor has source-drain section diffusive regions formed on a semiconductor substrate, and a gate electrode formed on a channel region between these source-drain section diffusive regions through a gate insulating film. One portion or all of the channel region of at least one MOS transistor within the basic cell region has an impurity concentration different from that in the channel region of another MOS transistor of the same conductivity type within the same basic cell. For example, a threshold voltage in the channel region of a MOS transistor is increased until about 6 volts by implanting ions into the channel region. No MOS transistor is operated at a power voltage such as 5 volts and separates MOS transistors on both sides thereof from each other.

Abstract: A semiconductor memory apparatus of an internal synchronization type uses a clock signal generated by detecting a change in address or control signal as an internal synchronization signal. The apparatus includes a dummy memory cell for fixing data thereto in advance; a precharging circuit for precharging an internal memory cell and the dummy cell; a precharge completion detector for detecting the completion of the precharging operation when a dummy bit line from the dummy cell attains a predetermined voltage level by the precharging operation, the precharge completion detector transmitting a signal for completing the precharging operation with respect to the precharging circuit; and a device for reading or writing data through a bit line to the memory cell by the completion of the precharging operation by the precharge completion detector.

Abstract: A multilevel sense circuit includes a memory MOSFET having one of at least two different current carrying states and a pair of reference MOSFETs one of which has one of the two current carrying states and the other of which has the other current carrying state. A first current supplying circuit is connected to the memory MOSFET for supplying a predetermined amount of current thereto when the memory MOSFET is activated. A second current supplying circuit is connected to the pair of reference MOSFETs and also to the first current supplying circuit, such that twice the aforementioned predetermined amount of current is supplied to the pair of reference MOSFETs when the memory MOSFET is activated. A multilevel semiconductor memory device includes a MOSFET having a channel whose width is varyingly set by providing a non-inverting region in a selected area of the channel by ion implantation.