Patents by Inventor Hikari Sano
Hikari Sano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8841753Abstract: A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.Type: GrantFiled: March 23, 2012Date of Patent: September 23, 2014Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Koji Koike
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Patent number: 8810039Abstract: A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.Type: GrantFiled: December 12, 2011Date of Patent: August 19, 2014Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Masao Takahashi, Hikari Sano, Yutaka Itoh, Koji Koike
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Patent number: 8237281Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.Type: GrantFiled: January 4, 2011Date of Patent: August 7, 2012Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
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Publication number: 20120181670Abstract: A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.Type: ApplicationFiled: March 23, 2012Publication date: July 19, 2012Applicant: Panasonic CorporationInventors: Koji TAKEMURA, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Koji Koike
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Patent number: 8164163Abstract: A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.Type: GrantFiled: February 12, 2008Date of Patent: April 24, 2012Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Koji Koike
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Publication number: 20120080780Abstract: A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.Type: ApplicationFiled: December 12, 2011Publication date: April 5, 2012Applicant: Panasonic CorporationInventors: Koji TAKEMURA, Hiroshige Hirano, Masao Takahashi, Hikari Sano, Yutaka Itoh, Koji Koike
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Patent number: 8134231Abstract: A semiconductor chip, including: a substrate including an front surface; an integrated circuit formed on the front surface and including a plurality of semiconductor elements; and a heat-radiating plug formed in a region of the substrate corresponding to at least one of the semiconductor elements. The heat-radiating plug is made of a material having a thermal conductivity greater than that of the substrate formed in a non-penetrating hole having its opening on a reverse surface of the substrate.Type: GrantFiled: January 5, 2009Date of Patent: March 13, 2012Assignee: Panasonic CorporationInventors: Hikari Sano, Yoshihiro Tomita, Takahiro Nakano
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Patent number: 8102056Abstract: A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.Type: GrantFiled: August 29, 2006Date of Patent: January 24, 2012Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Masao Takahashi, Hikari Sano, Yutaka Itoh, Koji Koike
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Publication number: 20110204487Abstract: A semiconductor device includes: a semiconductor substrate; a through electrode passing through the semiconductor substrate in a thickness direction of the semiconductor substrate; an internal electrode provided in a part of the top surface of the semiconductor substrate and electrically connected to the through electrode which reaches the part; a first protective film covering the top surface except a part of the internal electrode; a second protective film formed apart from the first protective film, on the part of the internal electrode, the part being not covered by the first protective film; and metal wiring formed on the back surface of the semiconductor substrate and electrically connected to the through electrode, the second main surface being on a side of the semiconductor substrate opposite the first main surface.Type: ApplicationFiled: May 4, 2011Publication date: August 25, 2011Applicant: PANASONIC CORPORATIONInventors: TAKAHIRO NAKANO, MASAKI UTSUMI, HIKARI SANO
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Publication number: 20110169118Abstract: The present invention is has an object of providing an optical device miniaturized while maintaining bonding strength between a semiconductor substrate and a light-transmissive plate, reducing possibility of warpage, and maintaining yields and design flexibility, a method of manufacturing the optical device, and an electronic apparatus. The optical device according to the present invention includes a semiconductor substrate having one surface in which a light-receiving element is formed; and a light-transmissive plate provided above the semiconductor substrate so as to cover the light-receiving element. The semiconductor substrate and the light-transmissive plate are partially bonded above a light-receiving unit of the semiconductor substrate. The light-receiving element is formed in the light-receiving unit.Type: ApplicationFiled: January 11, 2011Publication date: July 14, 2011Applicant: PANASONIC CORPORATIONInventor: Hikari SANO
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Publication number: 20110147905Abstract: In a semiconductor element, upper through-hole conductor portions and lower through-hole conductor portions are formed such that pore size A of the joint surface of the upper through-hole conductor portion and the lower through-hole conductor portion is smaller than pore size B of the upper through-hole conductor portion on the major surface of the semiconductor element and pore size C of the lower through-hole conductor portion on the other surface of the semiconductor element. Further, electrode portions are formed respectively on the top surfaces of the upper through-hole conductor portions and protrusions 4 are formed respectively on the top surfaces of the electrode portions. Moreover, an optical member pressed in contact with the protrusions is fixed on the semiconductor element with an adhesive.Type: ApplicationFiled: March 3, 2011Publication date: June 23, 2011Applicant: PANASONIC CORPORATIONInventors: Masaki Utsumi, Hikari Sano, Hiroaki Fujimoto, Yoshihiro Tomita
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Publication number: 20110147782Abstract: Provided is an optical device which has an increased rate of an area occupied by an effective optical region to an light-transmissive substrate and less noise due to reflection from a peripheral end face of the light-transmissive substrate. The optical device includes a semiconductor substrate in which a light-receiving element is formed and a light-transmissive substrate provided above the semiconductor substrate so as to cover the light-receiving element and fixed to the semiconductor substrate with an adhesive layer. The light-transmissive substrate has, in a peripheral end face, a curved surface which slopes so as to flare from an upper surface toward a lower surface.Type: ApplicationFiled: March 1, 2011Publication date: June 23, 2011Applicant: PANASONIC CORPORATIONInventors: Hikari SANO, Takahiro NAKANO
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Publication number: 20110147872Abstract: An optical device includes a semiconductor device, a light receiving part formed on the main surface of the semiconductor device, and a transparent board laminated above the main surface of the semiconductor device, with an adhesive material interposed between the transparent board and the main surface of the semiconductor device. A serrated part is formed on at least one of (i) the main surface that is of the transparent board and faces the semiconductor device and (ii) the back surface of the transparent board.Type: ApplicationFiled: March 1, 2011Publication date: June 23, 2011Applicant: Panasonic CorporationInventors: Daisuke INOUE, Kyoko FUJII, Takahiro NAKANO, Hikari SANO
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Publication number: 20110147871Abstract: To provide a semiconductor device and a method of manufacturing the same, which have a device structure ensuring high degrees of reliability and mass-productivity at low cost. A semiconductor device includes: a substrate including an imaging area and having a first main surface and a second main surface; an electrode formed on the first main surface; an external electrode formed on the second main surface; a conductive portion which is formed in a through hole penetrating the substrate, and electrically connects the electrode and the external electrode; an optical element which is placed on the first main surface and has a convex surface including a convex portion; and a light transmitting element which is bonded to the optical element so as to cover the convex portion and has a flat upper surface.Type: ApplicationFiled: February 28, 2011Publication date: June 23, 2011Applicant: PANASONIC CORPORATIONInventors: Masaki UTSUMI, Takahiro NAKANO, Hikari SANO
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Publication number: 20110147904Abstract: This invention provides a semiconductor device with increased moisture resistance. The semiconductor device includes: a semiconductor substrate; an optical element provided in a front surface of the semiconductor substrate; a light-transmissive substrate provided above the front surface of the semiconductor substrate; an adhesive layer provided between the front surface of the semiconductor substrate and a front surface of the light-transmissive substrate, and fixing the light-transmissive substrate to the semiconductor substrate; and an insulating film covering a lateral surface of said adhesive layer which is not in contact with the light-transmissive substrate and the semiconductor substrate.Type: ApplicationFiled: March 1, 2011Publication date: June 23, 2011Applicant: PANASONIC CORPORATIONInventor: Hikari SANO
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Patent number: 7960271Abstract: The present invention provides a semiconductor device that can suppresses poor connection caused by the variation of the heights of bumps during reflow heating, can be applied to a narrow array pitch, and can freely adjust the heights of the bumps.Type: GrantFiled: September 4, 2008Date of Patent: June 14, 2011Assignee: Panasonic CorporationInventors: Hideki Takehara, Yoshihiro Tomita, Seiji Fujiwara, Takahiro Nakano, Hikari Sano
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Publication number: 20110095430Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.Type: ApplicationFiled: January 4, 2011Publication date: April 28, 2011Applicant: PANASONIC CORPORATIONInventors: Koji TAKEMURA, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
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Patent number: 7888801Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.Type: GrantFiled: April 27, 2009Date of Patent: February 15, 2011Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
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Publication number: 20100176475Abstract: An optical device according to an aspect of the present invention includes: a semiconductor substrate layer including a plurality of elements; at least one optical component which is formed at the first principal surface side of the semiconductor substrate layer and transmits incident light of desired wavelength; and an interconnect layer formed on second principal surface of the semiconductor substrate layer. In the semiconductor substrate layer, (i) a photoelectric conversion element region is formed at a position corresponding to the at least one optical component, and (ii) at least one element among the plurality of elements is formed near the second principal surface. At least a part of the at least one optical component is formed as a part of the semiconductor substrate layer, and the interconnect layer includes the conductive material electrically connected to the photoelectric conversion element region and the at least one element.Type: ApplicationFiled: December 30, 2009Publication date: July 15, 2010Applicant: PANASONIC CORPORATIONInventors: Hikari Sano, Yoshihiro Tomita
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Publication number: 20100148294Abstract: An optical device such as an image sensor alleviates reduction in image quality caused by light reaching a peripheral circuit section other than a light receiving section. A semiconductor substrate includes an interconnect layer, a light receiving section provided with a plurality of light receiving elements on the interconnect layer, and a peripheral circuit section provided in a same layer as the light receiving section, and surrounding the light receiving section. Light entry elements are provided on a surface of the semiconductor substrate. A light shielding film is formed of a metal layer, and covers at least one part of a region corresponding to the peripheral circuit section. A first electrode is formed in the region corresponding to the peripheral circuit section, and in an opening of the light shielding film to be electrically isolated from the light shielding film.Type: ApplicationFiled: February 25, 2010Publication date: June 17, 2010Applicant: Panasonic CorporationInventors: Kyoko FUJII, Takahiro Nakano, Hikari Sano