Patents by Inventor Hikaru Shibahara
Hikaru Shibahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9478003Abstract: A display driver that receives display line data of plural display lines to perform drive control on a display panel includes a line memory for storing display line data which is supplied from the outside. The display driver includes a logic circuit that controls write and read-out of the display line data in and from the line memory, and sorts pixel data of the display line data using read out data from the line memory, to generate display drive data. Drive circuits drive the display panel in units of display lines based on the drive data which is output from the logic circuit. The drive circuits are separately arranged on both sides of the logic circuit and the line memory which are interposed therebetween. The storage capacity of the line memory corresponds to the number of lines smaller than the number of display lines of a display frame.Type: GrantFiled: September 20, 2014Date of Patent: October 25, 2016Assignee: Synaptics Display Devices GKInventors: Hikaru Shibahara, Hideaki Honda, Hiroki Takeuchi
-
Publication number: 20150097852Abstract: A display driver that receives display line data of plural display lines to perform drive control on a display panel includes a line memory for storing display line data which is supplied from the outside. The display driver includes a logic circuit that controls write and read-out of the display line data in and from the line memory, and sorts pixel data of the display line data using read out data from the line memory, to generate display drive data. Drive circuits drive the display panel in units of display lines based on the drive data which is output from the logic circuit. The drive circuits are separately arranged on both sides of the logic circuit and the line memory which are interposed therebetween. The storage capacity of the line memory corresponds to the number of lines smaller than the number of display lines of a display frame.Type: ApplicationFiled: September 20, 2014Publication date: April 9, 2015Inventors: Hikaru SHIBAHARA, Hideaki HONDA, Hiroki TAKEUCHI
-
Patent number: 8350832Abstract: The semiconductor IC device for display control disclosed herein aims to achieve a higher rate of memory access cycles without enhancing the current carrying capability of the memory device. The IC device is provided with a memory cell array capable to store display data, peripheral circuits to enable writing and reading of display data, and a control circuit which is able to control read and write operations from/to the memory cell array. The memory cell array comprises a plurality of memory blocks. The control circuit comprises a control logic which enables parallel processing of write operations in such a manner that, before completion of writing of data to one of the memory blocks, writing of data to another memory block is started. Write cycles are shortened by the parallel processing of write operations.Type: GrantFiled: November 20, 2007Date of Patent: January 8, 2013Assignee: Renesas Electronics CorporationInventors: Hirofumi Sonoyama, Sosuke Tsuji, Hikaru Shibahara
-
Patent number: 7742334Abstract: A memory cell of a memory array stores two bits. A memory array sense amplifier provides two bits in a verify operation. Two bits in a page buffer stores a write target value for the corresponding memory cell. Each bit in a mask buffer stores a value defining processing to be effected on the corresponding memory cell. A write driver applies a write pulse when the bit in the mask buffer corresponding to the selected memory cell is “0”. A verify circuit compares the two bits provided from the memory array sense amplifier with the corresponding two bits in the page buffer, and changes the corresponding bit in the mask buffer from “0” to “1” when the result of the comparison represents matching.Type: GrantFiled: June 25, 2007Date of Patent: June 22, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Tomoyuki Fujisawa, Hikaru Shibahara, Hidenori Mitani, Akihiko Kanda
-
Publication number: 20090129149Abstract: A memory cell of a memory array stores two bits. A memory array sense amplifier provides two bits in a verify operation. Two bits in a page buffer stores a write target value for the corresponding memory cell. Each bit in a mask buffer stores a value defining processing to be effected on the corresponding memory cell. A write driver applies a write pulse when the bit in the mask buffer corresponding to the selected memory cell is “0”. A verify circuit compares the two bits provided from the memory array sense amplifier with the corresponding two bits in the page buffer, and changes the corresponding bit in the mask buffer from “0” to “1” when the result of the comparison represents matching.Type: ApplicationFiled: June 25, 2007Publication date: May 21, 2009Inventors: Tomoyuki Fujisawa, Hikaru Shibahara, Hidenori Mitani, Akihiko Kanda
-
Patent number: 7518929Abstract: A memory cell of a memory array stores two bits. A memory array sense amplifier provides two bits in a verify operation. Two bits in a page buffer stores a write target value for the corresponding memory cell. Each bit in a mask buffer stores a value defining processing to be effected on the corresponding memory cell. A write driver applies a write pulse when the bit in the mask buffer corresponding to the selected memory cell is “0”. A verify circuit compares the two bits provided from the memory array sense amplifier with the corresponding two bits in the page buffer, and changes the corresponding bit in the mask buffer from “0” to “1” when the result of the comparison represents matching.Type: GrantFiled: June 25, 2007Date of Patent: April 14, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Tomoyuki Fujisawa, Hikaru Shibahara, Hidenori Mitani, Akihiko Kanda
-
Publication number: 20080122855Abstract: The semiconductor IC device for display control disclosed herein aims to achieve a higher rate of memory access cycles without enhancing the current carrying capability of the memory device. The IC device is provided with a memory cell array capable to store display data, peripheral circuits to enable writing and reading of display data, and a control circuit which is able to control read and write operations from/to the memory cell array. The memory cell array comprises a plurality of memory blocks. The control circuit comprises a control logic which enables parallel processing of write operations in such a manner that, before completion of writing of data to one of the memory blocks, writing of data to another memory block is started. Write cycles are shortened by the parallel processing of write operations.Type: ApplicationFiled: November 20, 2007Publication date: May 29, 2008Inventors: Hirofumi SONOYAMA, Sosuke Tsuji, Hikaru Shibahara
-
Publication number: 20080019176Abstract: A memory cell of a memory array stores two bits. A memory array sense amplifier provides two bits in a verify operation. Two bits in a page buffer stores a write target value for the corresponding memory cell. Each bit in a mask buffer stores a value defining processing to be effected on the corresponding memory cell. A write driver applies a write pulse when the bit in the mask buffer corresponding to the selected memory cell is “0”. A verify circuit compares the two bits provided from the memory array sense amplifier with the corresponding two bits in the page buffer, and changes the corresponding bit in the mask buffer from “0” to “1” when the result of the comparison represents matching.Type: ApplicationFiled: June 25, 2007Publication date: January 24, 2008Applicant: Renesas Technology Corp.Inventors: Tomoyuki Fujisawa, Hikaru Shibahara, Hidenori Mitani, Akihiko Kanda
-
Patent number: 7242611Abstract: A memory cell of a memory array stores two bits. A memory array sense amplifier provides two bits in a verify operation. Two bits in a page buffer stores a write target value for the corresponding memory cell. Each bit in a mask buffer stores a value defining processing to be effected on the corresponding memory cell. A write driver applies a write pulse when the bit in the mask buffer corresponding to the selected memory cell is “0”. A verify circuit compares the two bits provided from the memory array sense amplifier with the corresponding two bits in the page buffer, and changes the corresponding bit in the mask buffer from “0” to “1” when the result of the comparison represents matching.Type: GrantFiled: March 18, 2005Date of Patent: July 10, 2007Assignee: Renesas Technology Corp.Inventors: Tomoyuki Fujisawa, Hikaru Shibahara, Hidenori Mitani, Akihiko Kanda
-
Publication number: 20050232017Abstract: A memory cell of a memory array stores two bits. A memory array sense amplifier provides two bits in a verify operation. Two bits in a page buffer stores a write target value for the corresponding memory cell. Each bit in a mask buffer stores a value defining processing to be effected on the corresponding memory cell. A write driver applies a write pulse when the bit in the mask buffer corresponding to the selected memory cell is “0”. A verify circuit compares the two bits provided from the memory array sense amplifier with the corresponding two bits in the page buffer, and changes the corresponding bit in the mask buffer from “0” to “1” when the result of the comparison represents matching.Type: ApplicationFiled: March 18, 2005Publication date: October 20, 2005Inventors: Tomoyuki Fujisawa, Hikaru Shibahara, Hidenori Mitani, Akihiko Kanda