Abstract: A cooling structure for large electronic boards with closely-spaced heterogeneous die and packages is disclosed. The assembly includes a frame having a plurality of openings. The assembly further includes a cold plate mounted to the frame. The cold plate includes at least one inlet and at least one outlet and fluid channels in communication with the at least one inlet and the at least one outlet. The assembly further includes a heat sink mounted within each of the plurality of openings which in combination with sidewalls of the openings of the frame and the cold plate form individual compartments each of which are in fluid communication with the fluid channels.

Abstract: A cooling structure for large electronic boards with closely-spaced heterogeneous die and packages is disclosed. The assembly includes a frame having a plurality of openings. The assembly further includes a cold plate mounted to the frame. The cold plate includes at least one inlet and at least one outlet and fluid channels in communication with the at least one inlet and the at least one outlet. The assembly further includes a heat sink mounted within each of the plurality of openings which in combination with sidewalls of the openings of the frame and the cold plate form individual compartments each of which are in fluid communication with the fluid channels.

Abstract: An electronic package includes a carrier and a semiconductor chip. In a first aspect a lid is attached to the chip and subsequently the gap between the lid and the carrier is filled by a seal band that includes seal band material and a plurality of shim members. In another aspect, an interleaved seal band includes a pattern of a first type of seal band material and a second type of seal band material. In another aspect, the lid includes a plurality of surfaces at different topographies to reduce the thickness of the seal band between the topographic lid and the carrier. In yet another aspect the electronic package further includes a frame concentric with the chip. The lid is attached to the frame with a solder, epoxy or elastomer and placed on the chip with a thermal interface material. The seal band material is dispensed on the chip carrier and the frame is then moved towards the chip carrier allowing a minimum seal band thickness.

Abstract: An electronic package includes a carrier and a semiconductor chip. In a first aspect a lid is attached to the chip and subsequently the gap between the lid and the carrier is filled by a seal band that includes seal band material and a plurality of shim members. In another aspect, an interleaved seal band includes a pattern of a first type of seal band material and a second type of seal band material. In another aspect, the lid includes a plurality of surfaces at different topographies to reduce the thickness of the seal band between the topographic lid and the carrier. In yet another aspect the electronic package further includes a frame concentric with the chip. The lid is attached to the frame with a solder, epoxy or elastomer and placed on the chip with a thermal interface material. The seal band material is dispensed on the chip carrier and the frame is then moved towards the chip carrier allowing a minimum seal band thickness.

Abstract: Methods and apparatuses for reducing directional stress in an orthotropic encapsulation member of an electronic package may include attaching a stiffening frame to a carrier, the stiffening frame comprising a central opening to accept a semiconductor chip and a plurality of opposing sidewalls, electronically coupling the semiconductor chip to the carrier concentrically arranged within the central opening, and thermally contacting a directional heat spreader to the semiconductor chip, the directional heat spreader transferring heat from the semiconductor chip, wherein the directional heat spreader is shaped to reduce a directional stress along the opposing bivector direction.

Abstract: Methods and apparatuses for reducing directional stress in an orthotropic encapsulation member of an electronic package may include attaching a stiffening frame to a carrier, the stiffening frame comprising a central opening to accept a semiconductor chip and a plurality of opposing sidewalls, electronically coupling the semiconductor chip to the carrier concentrically arranged within the central opening, and thermally contacting a directional heat spreader to the semiconductor chip, the directional heat spreader transferring heat from the semiconductor chip, wherein the directional heat spreader is shaped to reduce a directional stress along the opposing bivector direction.

Abstract: In some embodiments, an apparatus includes a land grid array connector positioned above an electrical package. The apparatus also includes a channel housing positioned above the land grid array. The apparatus includes an electrical-to-optical transceiver positioned in an opening of a socket of the channel housing, wherein a tapered opening is formed above the electrical-to-optical transceiver in the channel housing after the electrical-to-optical transceiver is positioned in the opening of the socket of the channel housing. A gap of the tapered opening decreases progressively starting from the opening of the socket. A conductive wedge positioned in the gap of the tapered opening.

Abstract: An integrated circuit (IC) chip module includes a carrier, a stiffening frame, an IC chip, and a first directional heat spreader. A second directional heat spreader may further be arranged orthogonal to the first directional heat spreader. The carrier has a top surface and a bottom surface configured to be electrically connected to a motherboard. The stiffening frame includes an opening that accepts the IC chip and may be attached to the top surface of the carrier. The IC chip is concentrically arranged within the opening of the stiffening frame. The first directional heat spreader is attached to the stiffening frame and to the IC chip and generally removes heat in a first opposing bivector direction. When included in the IC chip module, the second directional heat spreader is attached to the stiffening frame and to the first directional heat spreader and generally removes heat in a second opposing bivector direction orthogonal to the first opposing bivector direction.

Abstract: A semiconductor device package which includes a semiconductor package, a semiconductor device joined to the semiconductor package; and a lid to be placed over the semiconductor device and joined to the semiconductor package. The lid includes: a block of a first material having a first surface and a second surface, the second surface facing the semiconductor device, the block having perforations extending between the first surface and the second surface; inserts for filling the perforations, each of the inserts being made of a second material, at least one of the inserts protrudes beyond the second surface towards the semiconductor device; and a bonding material to bond the inserts to the block so that the at least one of the inserts protrudes beyond the second surface towards the semiconductor device. Also included is a method of assembling a semiconductor device package.

Abstract: A cooling structure for large electronic boards with closely-spaced heterogeneous die and packages is disclosed. The assembly includes a frame having a plurality of openings. The assembly further includes a cold plate mounted to the frame. The cold plate includes at least one inlet and at least one outlet and fluid channels in communication with the at least one inlet and the at least one outlet. The assembly further includes a heat sink mounted within each of the plurality of openings which in combination with sidewalls of the openings of the frame and the cold plate form individual compartments each of which are in fluid communication with the fluid channels.

Abstract: In some embodiments, an apparatus includes a land grid array connector positioned above an electrical package. The apparatus also includes a channel housing positioned above the land grid array. The apparatus includes an electrical-to-optical transceiver positioned in an opening of a socket of the channel housing, wherein a tapered opening is formed above the electrical-to-optical transceiver in the channel housing after the electrical-to-optical transceiver is positioned in the opening of the socket of the channel housing. A gap of the tapered opening decreases progressively starting from the opening of the socket. A conductive wedge positioned in the gap of the tapered opening.

Abstract: Embodiments provide for a method for pluggable Land Grid Array (LGA) socket for high density interconnects. A method includes inserting an electrical-to-optical transceiver into an opening of a channel housing that is positioned above a land grid array connector located on an electrical package. After the electrical-to-optical transceiver is inserted into the channel housing, a tapered opening remains between an upper portion of the channel housing above the electrical-to-optical transceiver, wherein a gap of the tapered opening decreases progressively starting from the opening. The method includes inserting a conductive wedge into the gap of the tapered opening prior to communications through the electrical-to-optical transceiver between a component on the electrical package and a component external to the electrical package.

Abstract: An improved electronic module assembly and method of fabrication is disclosed. A patterned array of adhesive is deposited on a laminate, to which a chip is attached. Each region of adhesive is referred to as a lid tie. A lid is placed on the laminate, and is in contact with the lid ties. The lid ties serve to add stability to the laminate and reduce flexing during thermal processing and mechanical stress.

Abstract: A multi-chip module (MCM) package is provided and includes a substrate and a hat assembly. The substrate includes a surface on which chips of the MCM are re-workable. The hat assembly is configured to be non-hermetically sealed to the substrate. The hat assembly and the substrate are configured for tension-type disassembly in a dimension oriented substantially normally with respect to a plane of the substrate surface.

Abstract: An improved electronic module assembly and method of fabrication is disclosed. A patterned array of adhesive is deposited on a laminate, to which a chip is attached. Each region of adhesive is referred to as a lid tie. A lid is placed on the laminate, and is in contact with the lid ties. The lid ties serve to add stability to the laminate and reduce flexing during thermal processing and mechanical stress.

Abstract: A multi-chip electronic package and methods of manufacture are provided. The multi-chip package includes a plurality of chips mounted on a chip carrier. The multi-chip package further includes a lid mounted on the chip carrier using a bonding material or compression seal, and at least one single piston extending from the lid. Each piston covers an entirety of multiple chips of the plurality of chips.

Abstract: A multichip module includes a carrier, a stiffening frame, a plurality of semiconductor chips, and a plurality of covers. The carrier has a top surface and a bottom surface configured to be electrically connected to a motherboard. The stiffening frame includes a plurality of openings that accept the plurality of semiconductor chips and may be attached to the top surface of the carrier with an adhesive that absorbs dimensional changes between the stiffening frame and the carrier. The semiconductor chips are concentrically arranged within the plurality of openings of the stiffening frame and the plurality of covers are attached to the stiffening frame so as to enclose the plurality of openings.

Abstract: A multichip module includes a carrier, a stiffening frame, a plurality of semiconductor chips, and a plurality of covers. The carrier has a top surface and a bottom surface configured to be electrically connected to a motherboard. The stiffening frame includes a plurality of openings that accept the plurality of semiconductor chips and may be attached to the top surface of the carrier with an adhesive that absorbs dimensional changes between the stiffening frame and the carrier. The semiconductor chips are concentrically arranged within the plurality of openings of the stiffening frame and the plurality of covers are attached to the stiffening frame so as to enclose the plurality of openings.

Abstract: An improved electronic module assembly and method of fabrication is disclosed. A patterned array of adhesive is deposited on a laminate, to which a chip is attached. Each region of adhesive is referred to as a lid tie. A lid is placed on the laminate, and is in contact with the lid ties. The lid ties serve to add stability to the laminate and reduce flexing during thermal processing and mechanical stress.

Abstract: A multichip module includes a carrier, a stiffening frame, a plurality of semiconductor chips, and a plurality of covers. The carrier has a top surface and a bottom surface configured to be electrically connected to a motherboard. The stiffening frame includes a plurality of openings that accept the plurality of semiconductor chips and may be attached to the top surface of the carrier with an adhesive that absorbs dimensional changes between the stiffening frame and the carrier. The semiconductor chips are concentrically arranged within the plurality of openings of the stiffening frame and the plurality of covers are attached to the stiffening frame so as to enclose the plurality of openings.