Abstract: A novel nonlinear impulse sampler is presented that provides a clock sharpening circuit, sampling stage, and post-sampling block. The clock sharpening circuit sharpens the incoming clock while acting as a buffer, and the sharpened clock is fed to the input of the sampling stage. The impulse sampling stage has two main transistors, where one transistor generates the impulse and the other transistor samples the input signal. Post-sampling block processes the sampled signal and acts as a sample and hold circuit. The architecture uses an ultrafast transmission-line based inductive peaking technique to turn on a high-speed sampling bipolar transistor for a few picoseconds. It is shown that the sampler can detect impulses as short as 100 psec or less.

Abstract: A track and hold circuit includes a primary sampling capacitor, a primary switching transistor, and a cancellation transistor. The primary switching transistor is configured to provide a track state that connects an input signal to the primary sampling capacitor and a hold state that isolates the input signal from the primary sampling capacitor. The cancellation transistor is coupled to the primary sampling capacitor. The cancellation transistor is configured to inject a charge onto the primary sampling capacitor that cancels a charge injected onto the primary sampling capacitor by the primary switching transistor while the primary switching transistor is in the hold state.

Abstract: A novel nonlinear impulse sampler is presented that provides a clock sharpening circuit, sampling stage, and post-sampling block. The clock sharpening circuit sharpens the incoming clock while acting as a buffer, and the sharpened clock is fed to the input of the sampling stage. The impulse sampling stage has two main transistors, where one transistor generates the impulse and the other transistor samples the input signal. Post-sampling block processes the sampled signal and acts as a sample and hold circuit. The architecture uses an ultrafast transmission-line based inductive peaking technique to turn on a high-speed sampling bipolar transistor for a few picoseconds. It is shown that the sampler can detect impulses as short as 100psec or less.

Abstract: A track and hold circuit includes a primary sampling capacitor, a primary switching transistor, and a cancellation transistor. The primary switching transistor is configured to provide a track state that connects an input signal to the primary sampling capacitor and a hold state that isolates the input signal from the primary sampling capacitor. The cancellation transistor is coupled to the primary sampling capacitor. The cancellation transistor is configured to inject a charge onto the primary sampling capacitor that cancels a charge injected onto the primary sampling capacitor by the primary switching transistor while the primary switching transistor is in the hold state.

Abstract: An active cancellation system may provide a first and second transmission gates that are fed with an input signal and a complimentary signal, respectively. The first transmission gate may be switched on/off, and a second transmission gate may remain off at all times. When switched off, the first transmission gate may provide a leakage signal resulting from leakage in current, especially at high input frequencies, which is detrimental to performance. The complimentary signal fed to the second transmission gate is out of phase with the input signal, but identical in amplitude. Thus, second transmission gate may output a signal that can cancel out the leakage signal from the first transmission gate.

Abstract: An active cancellation system may provide a first and second transmission gates that are fed with an input signal and a complimentary signal, respectively. The first transmission gate may be switched on/off, and a second transmission gate may remain off at all times. When switched off, the first transmission gate may provide a leakage signal resulting from leakage in current, especially at high input frequencies, which is detrimental to performance. The complimentary signal fed to the second transmission gate is out of phase with the input signal, but identical in amplitude. Thus, second transmission gate may output a signal that can cancel out the leakage signal from the first transmission gate.