Abstract: A design tool inserts randomized delays into synchronizers for signals crossing from one clock domain to another. Rather than having a wide range of random delays to select from, each synchronizer's randomized delay is selected from only two possibilities. An added delay of either zero or one clock period of the new domain's clock is added as the randomized delay. The randomized delay causes the re-synchronized domain-crossing signal to become available either in the expected cycle or in the cycle following the expected cycle. Logic hazards caused by the domain-crossing signal can be detected and the possible results simulated. The synchronizer can be a series of two flip-flops, with the random delay added to the first flip-flop. Randomized delays of either one or none added periods of the clock can also be added to multi-cycle signals within one clock domain that have two or more clock cycles to propagate.

Abstract: A graphics system stores graphics data in a dynamic-random-access memory (DRAM) and in a faster static random-access memory (SRAM). A refresh controller reads pixel data from a frame buffer that is usually in the faster SRAM, while one or more video overlay engines read graphics objects from the DRAM. However, large frame buffers may be partially stored in the DRAM. Some of the graphics data read by the video overlay engine may reside in the SRAM. A dual-layer arbiter receives requests from the refresh controller and the overlay engines for access to the SRAM and DRAM. When two requestors request the same memory device, the dual-layer arbiter arbitrates access. However, often the requests are to different memory devices and the dual-layer arbiter can pass the requests through without delay, since separate buses to the DRAM and SRAM can be used simultaneously.

Abstract: A graphics system stores graphics data in a dynamic-random-access memory (DRAM) and in a faster static random-access memory (SRAM). A refresh controller reads pixel data from a frame buffer that is usually in the faster SRAM, while one or more video overlay engines read graphics objects from the DRAM. However, large frame buffers may be partially stored in the DRAM. Some of the graphics data read by the video overlay engine may reside in the SRAM. A dual-layer arbiter receives requests from the refresh controller and the overlay engines for access to the SRAM and DRAM. When two requestors request the same memory device, the dual-layer arbiter arbitrates access. However, often the requests are to different memory devices and the dual-layer arbiter can pass the requests through without delay, since separate buses to the DRAM and SRAM can be used simultaneously.