Abstract: The described techniques implement an electronic design with transistor level satisfiability models by identifying a plurality of channel connected components of an electronic design for sensitization. These techniques further determine a set of transistor level satisfiability (SAT) models for the plurality of channel connected components of the electronic design and transform the plurality of channel connected components into a set of conjunctive normal form (CNF) formulae using at least the set of transistor level SAT models. The plurality of channel connected components of the electronic design may be sensitized at least by determining one or more satisfying assignments with the set of CNF formulae. These techniques may also generate transistor level satisfiability (SAT) logic models and transistor level SAT state models for a circuit component based in part or in whole upon design specifications and one or more characteristics of the circuit component.

Abstract: Various embodiments scalable statistical library characterization for electronic designs by identifying an electronic design, performing circuit simulations on strongly connected components on a component-by-component basis, performing the logic cone analysis on the entire electronic design, and performing combinations of influences on the electronic design caused by variations of parameters. Some embodiments perform simulations on one or more stronger parameters or the strongest parameter of a circuit component and use the simulation results to calibrate the predicted behaviors of one or more remaining circuit components of the electronic design. Various statistical or mathematical techniques may be used for performing the combinations of influences on the electronic design caused by variations of parameters. The techniques described are scalable with the increase in complexities and sizes of electronic designs while reducing or minimizing the impact on sensitivity accuracy.