Abstract: A Real Time Protocol (RTP) packet handler includes a protocol processor (44) coupled to a communications medium (26) and a central processing unit (CPU) (46). The protocol processor (44) receives IP packets (24) transmitted over the communications medium (26). Operating system (OS) software executing on the CPU (46) controls the operation of the protocol processor (44) via a host interface (57) and a dual port RAM (58). A switch (50) routes RTP type IP packets to a RTP handler module (48) running on the protocol processor (44). The RTP packet handler module (48) processes RTP packets. Non-RTP packets are processed by the OS software (46).

Abstract: An arrangement and method for producing a plurality of pulse width modulated outputs, comprising: receiving values representative of durations of pulses to be generated at the outputs (210); producing values representative of the time differences (230) between transitions of pulses to be produced; and producing transitions in the pulses in the plurality of channels at times corresponding to the time Difference values.

Abstract: A method and apparatus for reducing power consumption in a portable electronic device (100) with an LCD screen (104) and operating with a CPU (114) switchable between a high power mode and a low power mode. When input commences on a surface of the LCD screen (104), an interrupt signaler (108) generates a first interrupt signal to an interrupt controller (112). Upon receiving the first interrupt signal, the interrupt controller (112) switches the CPU (114) from the low power mode to the high power mode, turning on at least one detection panel (106) coupled to the LCD screen (104) and to an ADC (110). When input ceases on the surface, the interrupt signaler (108) generates a second interrupt signal to switch the CPU (114) from the high power mode to the low power mode, turning off the at least one detection panel (106) and the ADC (110).

Abstract: A data processing system (20) has a display controller (28) that uses bus arbitration and data bursting to supply display data for refreshing an LCD screen (49), utilizing a system memory (30) instead of a separate video RAM. A screen DMA (58) fills a line buffer (60) with display data from the system memory (30) in bursts of a predetermined number of words. The screen DMA (58) receives a faster clocking signal than is used by the CPU (22). This allows the screen DMA (58) to run faster than the CPU (22) to reduce bandwidth needed to retrieve the display data. In addition, if the CPU (22) clock frequency is changed for power management purposes, the LCD screen (49) is not affected since it uses a different clock. By using the system memory (30) for storing display data, pin count, packaging costs, and board space are reduced.

Abstract: When an external reset signal EXRST is asserted received by a reset unit (6), it is synchronised with an internal clock to produce an internal reset signal INRST, which is applied to a CPU (4) and other modules in the circuit to reset them. While the internal reset signal INRST is being applied to the CPU, the rate of a refresh signal being generated by a DRAM controller (7) for refreshing data in DRAM (3) is increased. Then, when the external reset signal EXRST is disabled, a delayed reset signal DLYRST is generated and applied to the DRAM controller (7) so that it is reset. The CPU, being already reset, can then quickly reconfigure the DRAM controller and re-enable it to resume refreshing the DRAM (4), thus maintaining the data in the DRAM.

Abstract: A data processing system (20) has a multi-function scalable parallel I/O port (44). The I/O port (44) includes a plurality of I/O port circuits (55, 56) coupled to I/O terminals (67, 77) . The I/O port (44) can multiplex two functions onto one terminal (67,77) . One function is an I/O function and the other function is function under the control of an internal module (22, 24, 26, 32) connected to the terminal (67, 77). Each I/O port circuit (55, 56) has either a pull-down circuit (68) or a pull-up circuit (78) coupled to the terminal (67, 77). The pull-up and pull-down circuits (78, 68) are controllable using a control register (81, 82). The pull-up and pull-down circuits (78, 68) for each terminal (67, 77) can be individually selected, and function whether the I/O port (44) is selected or deselected.

Abstract: In a portable electronic device, a method and apparatus for providing a predetermined portion of a limited resource from a programmable resource allocators (PRAs) (240) to a processor (22) to execute a task (210) optimally. The processor (22) programming the PRA with a resource utilization input (RUI) (250) prior to executing the task (210). The RUI (250) stored in a task descriptor (220), and the task descriptor (220) and the task (210) stored in the memory (200).