Abstract: According to one embodiment, there is provided an optical disk apparatus including a detecting unit which reads a reflective light from an optical disk and outputs a read signal, a decoder which decodes the read signal from the detecting unit, an extracting unit which extracts from the read signal the first and second specification information of the same content recorded in first and second areas on the optical disk, a processor which compares the first specification information with the second specification information and processes the specification information based on the comparison result, and a controller which controls the detecting unit or the decoder, based on the specification information processed by the processor.

Abstract: According to one embodiment, a frequency detector detects a frequency error between a frequency of a reproduction signal supplied from an analog to digital converter and a frequency of a clock for conversion. A loop filter controls an oscillation frequency of a voltage control oscillator based on the frequency error and a phase error detected by a phase comparator. An adaptive equalizer equalizes a waveform of the reproduction signal supplied from the analog to digital converter to obtain a response of a predetermined PR class. A Viterbi decoder decodes the waveform equalized signal into binary data by maximum likelihood sequence estimation. A clock supply control circuit stops supply of a clock to at least the phase comparator, the adaptive equalizer and the Viterbi decoder in a case where the frequency error is larger than a designated error.

Abstract: A plurality of defect management areas (DMA set groups 1 to N) are used in a ring form in such a manner that defect management information of the DMA replaces and is recorded in the next spare area while the DMA is supposed to be still sufficiently rewritable (e.g., currently used DMA sets #1-1 to #4-1 are replaced with the next DMA sets #1-2 to #4-2), and a process returns to a first defect management area again at a time when transition of the defect management information ends up to a last spare area (DMA sets #1-N to #4-N).

Abstract: A wireless communication device for performing wireless communications between a plurality of terminals embraced by a multi-hop wireless communication network, includes first communication means for transmitting and receiving neighboring terminal information at a first speed to and from non-neighboring terminals other than neighboring terminals of a self-terminal, and second communication means for transmitting and receiving information other than at least the neighboring terminal information at a second speed higher than the first speed to and from the neighboring terminals to the self-terminal.

Abstract: An input distribution packet switch network includes a plurality of 2×2 switch elements and packet input modules for the switch network. The switch elements are arranged in multistage and connected in accordance with Shuffle type topology to constitute a N×N switch network (N=2k, k: integer number of 2 and over). The links of the leftmost and rightmost switch elements are connected to one another so that the N×N switch network can have a ring architecture. The packet input modules are distributed laterally in the switch network.