Abstract: A physical property map image generation apparatus performs: acquiring, for each pattern of a material, physical property information indicating a physical property quantity for each physical property of a product; and generating a self-organizing map and a physical property map image. A position in a map space and a physical property vector indicating a value related to a physical property quantity for each type of physical properties of the product are assigned to each node on the self-organizing map. On the physical property map image 40, each of the nodes arranged in the map space is represented by a color assigned to that node. For each node, each of two or three base color components of a color assigned to the node is determined based on a value that a physical property vector assigned to that node indicates for a physical property corresponding to that base color.

Abstract: A singular material detection apparatus (2000) acquires, for each of a plurality of materials (60), material specification information (10) representing material specifications of the material (60) and physical property information (20) indicating physical properties of a product (70) that can be generated by using the material (60). The singular material detection apparatus (2000) generates a self-organizing map (30) by using the physical property information (20). The singular material detection apparatus (2000) assigns each of pieces of material specification information (10) to one of nodes based on the physical property information (20) corresponding to that piece of the material specification information (10). Then, the singular material detection apparatus (2000) detects, from among the nodes to which the pieces of material specification information (10) are assigned, a singular node located at a singular position in a map space.

Abstract: A map image generation apparatus acquires material specification information representing a material specification of a material and physical property information representing a physical property of a product. The map image generation apparatus generates a self-organizing map by using the physical property information. A position in a map space, and a physical property vector indicating, for each of a plurality of types of physical properties of the product, a value related to a physical property quantity of the physical property are assigned to each of nodes on the self-organizing map. The map image generation apparatus assigns, by using the material specification information, a specification vector indicating a value related to the material specification to each of the nodes. The map image generation apparatus generates a map image in which the nodes are clustered or colored based on the specification vectors.

Abstract: Provided is a technology that suppresses the removal of collector layers in the planarization process while suppressing the snapback phenomenon. A semiconductor device related to a technology disclosed in the present specification includes a drain layer of first conductivity type in a part of a lower surface a drift layer, a plurality of collector layers of second conductivity type in parts of the lower surface of the drift layer, and a dummy layer of the first conductivity type interposed between the plurality of collector layers in parts of the lower surface of the drift layer, in which a width of the dummy layer 3 in a first direction, which is the direction in which the dummy layer is interposed between the plurality of collector layers, is narrower than a width of the drain layer in the first direction.

Abstract: A semiconductor device that includes a semiconductor layer disposed on a semiconductor substrate, a first semiconductor region provided in an upper layer portion of the semiconductor layer, a second semiconductor region provided in an upper layer portion of the first semiconductor region, a gate insulation film, a gate electrode, a first main electrode that is provided on an interlayer insulation film that covers the gate electrode and that is electrically connected to the second semiconductor region via a contact hole, and a second main electrode disposed on a second main surface of the semiconductor substrate. The first main electrode includes an underlying electrode film connected to the second semiconductor region via the contact hole, and a copper film provided on the underlying electrode film. The copper film includes at least a portion that serves as a stress relaxation layer having a smaller grain size than the other portion of the copper film.

Abstract: An electrode is disposed on a semiconductor layer. A polyimide layer has an opening disposed on the electrode, covers the edge of the electrode, and extends onto the electrode. A copper layer is disposed on the electrode within the opening, and located away from the polyimide layer on the electrode. A copper wire has one end joined on the copper layer.

Abstract: The object of the present invention is to suppress cracks in the interlayer insulating film attributed to growth of Cu crystal grains. The semiconductor device (101) includes a source region (5), an interlayer insulating film (7) made of silicon oxide, having an opening portion, and formed on the source region (5), a Cu electrode (1) electrically connected to the source region (5) through the opening portion of the interlayer insulating film (7) and an end portion thereof is located on the interlayer insulating film (7) inside an end portion of the interlayer insulating film (7), and a stress relieving layer (13) formed between the Cu electrode (1) and the interlayer insulating film (7), made of a material having a higher fracture toughness value than the interlayer insulating film (7), and extending from the inside to the outside of the end portion of the Cu electrode (1).

Abstract: An electrode is disposed on a semiconductor layer. A polyimide layer has an opening disposed on the electrode, covers the edge of the electrode, and extends onto the electrode. A copper layer is disposed on the electrode within the opening, and located away from the polyimide layer on the electrode. A copper wire has one end joined on the copper layer.

Abstract: A method for manufacturing a semiconductor device includes: a process of forming a Cu wiring electrode by a plating method above a semiconductor element using a wide bandgap semiconductor as a base material; a reducing process of reducing the Cu wiring electrode under a NH3 atmosphere; a heating process of heating the Cu wiring electrode at the same time as the reducing process; a process of forming a diffusion prevention film covering the Cu wiring electrode after the heating process; and a sealing process of covering the diffusion prevention film with an organic resin film.

Abstract: A semiconductor device that includes a semiconductor layer disposed on a semiconductor substrate, a first semiconductor region provided in an upper layer portion of the semiconductor layer, a second semiconductor region provided in an upper layer portion of the first semiconductor region, a gate insulation film, a gate electrode, a first main electrode that is provided on an interlayer insulation film that covers the gate electrode and that is electrically connected to the second semiconductor region via a contact hole, and a second main electrode disposed on a second main surface of the semiconductor substrate. The first main electrode includes an underlying electrode film connected to the second semiconductor region via the contact hole, and a copper film provided on the underlying electrode film. The copper film includes at least a portion that serves as a stress relaxation layer having a smaller grain size than the other portion of the copper film.

Abstract: A method for manufacturing a semiconductor device includes: a process of forming a Cu wiring electrode by a plating method above a semiconductor element using a wide bandgap semiconductor as a base material; a reducing process of reducing the Cu wiring electrode under a NH3 atmosphere; a heating process of heating the Cu wiring electrode at the same time as the reducing process; a process of forming a diffusion prevention film covering the Cu wiring electrode after the heating process; and a sealing process of covering the diffusion prevention film with an organic resin film.

Abstract: A method of manufacturing a silicon carbide semiconductor device is provided. The method suppresses the increase in the number of manufacturing steps and is capable of suppressing the degradation of ohmic characteristics of an alloy layer with respect to a semiconductor substrate. The method includes a step of forming a metal layer made of a first metal on a semiconductor substrate made of silicon carbide; a step of forming a metal nitride film obtained by nitriding a second metal on the metal layer; a step of directing a laser light through the metal nitride film to form a layer of an alloy of silicon carbide in the semiconductor substrate and the first metal in the metal layer; and a step of forming an electrode on the metal nitride film.

Abstract: A semiconductor device capable of inhibiting oxidation of a Cu wiring even in a high temperature operation. The semiconductor device includes a semiconductor substrate having a main surface, a Cu electrode which is selectively formed on a side of the main surface of the semiconductor substrate, an antioxidant film formed on an upper surface of the Cu electrode except an end portion thereof, an organic resin film which is formed on the main surface of the semiconductor substrate and covers a side surface of the Cu electrode and the end portion of the upper surface thereof, and a diffusion prevention film formed between the organic resin film and the main surface of the semiconductor substrate and between the organic resin film and the side surface and the end portion of the upper surface of the Cu electrode, being in contact therewith.

Abstract: A method of manufacturing a silicon carbide semiconductor device is provided. The method suppresses the increase in the number of manufacturing steps and is capable of suppressing the degradation of ohmic characteristics of an alloy layer with respect to a semiconductor substrate. The method includes a step of forming a metal layer made of a first metal on a semiconductor substrate made of silicon carbide; a step of forming a metal nitride film obtained by nitriding a second metal on the metal layer; a step of directing a laser light through the metal nitride film to form a layer of an alloy of silicon carbide in the semiconductor substrate and the first metal in the metal layer; and a step of forming an electrode on the metal nitride film.

Abstract: A semiconductor device capable of inhibiting oxidation of a Cu wiring even in a high temperature operation. The semiconductor device includes a semiconductor substrate having a main surface, a Cu electrode which is selectively formed on a side of the main surface of the semiconductor substrate, an antioxidant film formed on an upper surface of the Cu electrode except an end portion thereof, an organic resin film which is formed on the main surface of the semiconductor substrate and covers a side surface of the Cu electrode and the end portion of the upper surface thereof, and a diffusion prevention film formed between the organic resin film and the main surface of the semiconductor substrate and between the organic resin film and the side surface and the end portion of the upper surface of the Cu electrode, being in contact therewith.

Abstract: A semiconductor device capable of reducing ON-resistance changes with temperature, including a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type formed on the semiconductor substrate, a first well region of a second conductivity type formed in the front surface of the drift layer, a second well region of the second conductivity type formed in the front surface of the drift layer, and a gate structure that is formed on the front surface of the drift layer and forms a channel in the first well region and a channel in the second well region. A channel resistance of the channel formed in the first well region has a temperature characteristic that the channel resistance decreases with increasing temperature and a channel resistance of the channel formed in the second well region has a temperature characteristic that the channel resistance increases with increasing temperature.

Abstract: A semiconductor device capable of reducing ON-resistance changes with temperature, including a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type formed on the semiconductor substrate, a first well region of a second conductivity type formed in the front surface of the drift layer, a second well region of the second conductivity type formed in the front surface of the drift layer, and a gate structure that is formed on the front surface of the drift layer and forms a channel in the first well region and a channel in the second well region. A channel resistance of the channel formed in the first well region has a temperature characteristic that the channel resistance decreases with increasing temperature and a channel resistance of the channel formed in the second well region has a temperature characteristic that the channel resistance increases with increasing temperature.