Patents by Inventor Hiroaki Okudaira

Hiroaki Okudaira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8907475
    Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: December 9, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hanae Shimokawa, Tasao Soga, Hiroaki Okudaira, Toshiharu Ishida, Tetsuya Nakatsuka, Yoshiharu Inaba, Asao Nishimura
  • Publication number: 20130286621
    Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.
    Type: Application
    Filed: June 21, 2013
    Publication date: October 31, 2013
    Inventors: Hanae SHIMOKAWA, Tasao SOGA, Hiroaki OKUDAIRA, Toshiharu ISHIDA, Tetsuya NAKATSUKA, Yoshiharu INABA, Asao NISHIMURA
  • Patent number: 8503189
    Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: August 6, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hanae Shimokawa, Tasao Soga, Hiroaki Okudaira, Toshiharu Ishida, Tetsuya Nakatsuka, Yoshiharu Inaba, Asao Nishimura
  • Publication number: 20100214753
    Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.
    Type: Application
    Filed: May 4, 2010
    Publication date: August 26, 2010
    Inventors: Hanae SHIMOKAWA, Tasao Soga, Hiroaki Okudaira, Toshiharu Ishida, Tetsuya Nakatsuka, Yoshiharu Inaba, Asao Nishimura
  • Patent number: 7709746
    Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: May 4, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Hanae Shimokawa, Tasao Soga, Hiroaki Okudaira, Toshiharu Ishida, Tetsuya Nakatsuka, Yoshiharu Inaba, Asao Nishimura
  • Publication number: 20060115994
    Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.
    Type: Application
    Filed: January 13, 2006
    Publication date: June 1, 2006
    Inventors: Hanae Shimokawa, Tasao Soga, Hiroaki Okudaira, Toshiharu Ishida, Tetsuya Nakatsuka, Yoshiharu Inaba, Asao Nishimura
  • Patent number: 7013564
    Abstract: A method of producing an electronic device by connecting a lead of a semiconductor device with an electrode of a circuit board to form a bonded structure. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: March 21, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Hanae Shimokawa, Tasao Soga, Hiroaki Okudaira, Toshiharu Ishida, Tetsuya Nakatsuka, Yoshiharu Inaba, Asao Nishimura
  • Patent number: 6960396
    Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: November 1, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Hanae Shimokawa, Tasao Soga, Hiroaki Okudaira, Toshiharu Ishida, Tetsuya Nakatsuka, Yoshiharu Inaba, Asao Nishimura
  • Publication number: 20020163085
    Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.
    Type: Application
    Filed: July 3, 2002
    Publication date: November 7, 2002
    Inventors: Hanae Shimokawa, Tasao Soga, Hiroaki Okudaira, Toshiharu Ishida, Tetsuya Nakatsuka, Yoshiharu Inaba, Asao Nishimura
  • Publication number: 20020019077
    Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.
    Type: Application
    Filed: October 9, 2001
    Publication date: February 14, 2002
    Inventors: Hanae Shimokawa, Tasao Soga, Hiroaki Okudaira, Toshiharu Ishida, Tetsuya Nakatsuka, Yoshiharu Inaba, Asao Nishimura
  • Publication number: 20020009610
    Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.
    Type: Application
    Filed: October 9, 2001
    Publication date: January 24, 2002
    Inventors: Hanae Shimokawa, Tasao Soga, Hiroaki Okudaira, Toshiharu Ishida, Tetsuya Nakatsuka, Yoshiharu Inaba, Asao Nishimura
  • Patent number: 5510976
    Abstract: A control system is for accelerating stabilization of a chaotic state of a controlled system into a desired periodic state. In the control system, the SOGY algorithm is extended to permit selection of a region on a chaotic attractor as a target, so that the SOGY algorithm can be successfully combined with the OGY algorithm for the purpose of stabilization of the controlled system in the periodic state. Also, the method of nonlinear prediction is introduced so as to secure the effectiveness of the SOGY algorithm. Further, an uncertainty of prediction is taken into consideration so as to eliminate unnecessary control and to improve the effectiveness of the SOGY algorithm.
    Type: Grant
    Filed: February 8, 1994
    Date of Patent: April 23, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Tanaka, Hiroshi Okamoto, Masayoshi Naito, Shin-ichiro Umemura, Yasuo Morooka, Masahiro Kayama, Hiroaki Okudaira
  • Patent number: 5202151
    Abstract: The present invention relates to an electroless gold plating solution, a method of plating by using the same, and an electronic device plated with gold by using the same.According to the present electroless gold plating solution, the plating solution components contain no cyanide ions, the amount of a reducing agent used is small, and gold plating can be carried out without causing the gold plating on conducting paths having a fine interval between them to short-circuit the conducting paths.Therefore, according to the method of gold plating by using said electroless gold plating solution, a plating method that is safe in the plating work and in the treatment of its waste liquor can be accomplished. The method has a feature that the method can provide an electronic device on which parts can be mounted highly densely, and wherein the joint reliability to the parts is high.
    Type: Grant
    Filed: June 4, 1990
    Date of Patent: April 13, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Jiro Ushio, Osamu Miyazawa, Akira Tomizawa, Hitoshi Yokono, Naoya Kanda, Naoko Matsuura, Setsuo Ando, Hiroaki Okudaira
  • Patent number: 5198273
    Abstract: The present invention provides an electroless gold plating solution comprising essentially gold ions, a complexing agent, and a reducing agent, characterized by further containing a reduction promoter which has a function of giving electrons to an oxidant, the oxidant being produced from oxidation of the reducing agent with the gold ions being reduced, to change the oxidant to the original reducing agent. The present invention also provides a process for conducting electroless gold plating by bringing a substrate into contact with the electroless gold plating solution. The plating solution is excellent in the stability for gold plating of high deposition rate. Thus the present invention allows the electroless gold plating to be performed stably at a higher deposition rate.
    Type: Grant
    Filed: September 11, 1990
    Date of Patent: March 30, 1993
    Assignees: Hitachi, Ltd., Hitachi Chemical Company, Ltd.
    Inventors: Setsuo Ando, Jiro Ushio, Takashi Inoue, Hiroaki Okudaira, Takeshi Shimazaki, Hitoshi Yokono
  • Patent number: 4963974
    Abstract: The present invention relates to an electroless gold plating solution, a method of plating by using the same, and an electronic device plated with gold by using the same.According to the present electroless gold plating solution, the plating solution components contain no cyanide ions, the amount of a reducing agent used is small, and gold plating can be carried out without causing the gold plating on conducting paths having a fine interval between them to short-circuit the conducting paths.Therefore, according to the method of gold plating by using said electroless gold plating solution, a plating method that is safe in the plating work and in the treatment of its waste liquor can be accomplished. The method has a feature that the method can provide an electronic device on which parts can be mounted highly densely, and wherein the joint reliability to the parts is high.
    Type: Grant
    Filed: April 20, 1988
    Date of Patent: October 16, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Jiro Ushio, Osamu Miyazawa, Akira Tomizawa, Hitoshi Yokono, Naoya Kanda, Naoko Matsuura, Setsuo Ando, Hiroaki Okudaira
  • Patent number: 4913769
    Abstract: The present invention relates to an element comprising a superconductive material or a wiring formation technique. In a thin film wiring board in which a superconductive material is used as a conductor, annealing should be conducted at a high temperature in an oxygen atmosphere after formation of a film in order to convert the conductor portion into a superconductive material, which makes it necessary to use an inorganic oxide as the insulating film. This brought about a problem that the etching of the second and subsequent insulation layers causes a damage to the wiring and insulation layer provided thereunder.In the present invention, an over-etching preventing layer is provided on a wiring layer provided under the second and subsequent insulation layers in order to solve the problem in question.The present invention brings about an effect of realizing the formation of a multi-layered wiring layer by making use of a superconductive material.
    Type: Grant
    Filed: August 4, 1988
    Date of Patent: April 3, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Naoya Kanda, Takayoshi Sowa, Tetsuya Yamazaki, Hiroaki Okudaira
  • Patent number: 4735853
    Abstract: Disclosed is a magnetic recording medium in which an underlayer formed below a magnetic medium, in which a signal is written, is composed of a nickel alloy comprising 0.05 to 10 atom % of tungsten and 14 to 30 atom % of phosphorus. In this magnetic recording medium, the temperature for formation of magnetic medium and the temperature for formation of a protective film can be elevated over the levels adopted in the conventional techniques. Therefore, the magnetic characteristics and abrasion resistance can be improved. Furthermore, the magnetic recording medium is excellent in the mechanical strength and corrosion resistance. Accordingly, the reliability of the magnetic medium can be highly improved.
    Type: Grant
    Filed: May 15, 1986
    Date of Patent: April 5, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Hiroaki Okudaira, Hitoshi Oka, Masako Fujisawa, Yoshio Gobara, Nobuo Nakagawa