Abstract: A liquid discharging apparatus capable of performing printing on a medium having a short-side width of A3 or greater, the apparatus including a head unit which includes an exchangeable print head including a discharge unit that discharges a liquid through driving of a drive element, a detection circuit which detects that exchanging of the print head is possible, and a wiring substrate which is provided with a connector and is electrically connected to the print head via the connector, a drive circuit which outputs a drive signal for driving the drive element, and a cable which is connected to the wiring substrate and transfers the drive signal to the print head.

Abstract: A liquid discharging apparatus capable of performing printing on a medium having a short-side width of A3 or greater, the apparatus including a head unit which includes an exchangeable print head including a discharge unit that discharges a liquid through driving of a drive element, a detection circuit which detects that exchanging of the print head is possible, and a wiring substrate which is provided with a connector and is electrically connected to the print head via the connector, a drive circuit which outputs a drive signal for driving the drive element, and a cable which is connected to the wiring substrate and transfers the drive signal to the print head.

Abstract: A data transfer control device includes an OTG (state) controller which controls a plurality of states including a host operation state and a peripheral operation state, a host controller which is connected with a transceiver during the host operation, a peripheral controller which is connected with the transceiver during the peripheral operation, a register section including transfer condition registers which are used commonly during the host operation and the peripheral operation, and a buffer controller which controls access to a packet buffer used commonly by the host controller and the peripheral controller. Pipe regions PIPE0 to PIPEe are allocated in the packet buffer during the host operation, and endpoint regions EP0 to EPe are allocated in the packet buffer during the peripheral operation.

Abstract: A transaction is automatically issued with respect to one of end points and data is automatically transferred while the remaining data size of the transfer data is calculated based on the total size and the maximum packet size. When the remaining data size in the current transaction is less than the maximum packet size, the next transaction is issued automatically, and a short packet is transferred automatically to nest one of the end points. When the payload size of the packet to be transferred by the current transaction is the maximum packet size and the remaining data size of the transfer data is zero, a short packet of zero data length is transferred automatically to the next one of the end points. When DMA transfer is complete and the remaining data to be transferred is zero, a short packet of zero data length is transferred automatically in response to an IN token from a host. Data transfer according to USB On-The-Go is performed.

Abstract: A data transfer control device for data transfer through a bus, includes: a buffer controller which controls access to a packet buffer which stores data; and a transfer controller which controls transfer of the data stored in the packet buffer. A transaction for performing data transfer with a transfer destination is issued, and when a negative acknowledgment (NAK) response to the issued transaction is returned from the transfer destination, issuance of a retransmission transaction for the NAK response is allowed after waiting for a predetermined skip timing.

Abstract: An oscillation circuit generates a reference clock signal for a clock signal supplied to each section of a data transfer control device. In a clock output control circuit, a clock command is decoded by a clock command decoder and oscillation of the oscillation circuit is controlled. The data transfer control device including a clock control circuit transfers data as a host or a peripheral in a state being set to either a self-powered first device or a second device which can operate by using a power supply on a bus. The oscillation operation of the oscillation circuit is suspended in an idle state of the second device.

Abstract: In a clock generating circuit, clocks generated therein are distributed by a clock distribution control circuit for every circuit block. In a clock output control circuit, a clock command is decoded by a clock command decoder and output of the clocks is controlled for every circuit block. A data transfer control device having a clock control circuit functions as a first device or a second device to transfer data as a host or a peripheral. When the data transfer control device function as a second device and in an idle state, it controls clock output to a state controller which controls switching between a host function and a peripheral function.

Abstract: A plurality of pipe regions PIPE0 to PIPEe in which data transferred to and from endpoints is stored are allocated in a packet buffer (FIFO). Transfer condition information on data transfer between the pipe regions and the endpoints is set in transfer condition registers TREG0 to TREGe in a register section. A host (transfer) controller automatically generates a transaction for each of the endpoints based on the transfer condition information (total size, maximum packet size, transfer direction, number of continuous execution times, token issue interval, and the like) set in the transfer condition registers, and automatically transfers data between each pipe region and the endpoint. An OTG (state) controller which controls a state of USB On-The-Go is provided. The pipe regions are allocated in the packet buffer during a host operation.

Abstract: A data transfer control device for data transfer through a bus, includes: a buffer controller which controls access to a packet buffer which stores data; and a transfer controller which controls transfer of the data stored in the packet buffer. A transaction for performing data transfer with a transfer destination is issued, and when a negative acknowledgment (NAK) response to the issued transaction is returned from the transfer destination, issuance of a retransmission transaction for the NAK response is allowed after waiting for a predetermined skip timing.

Abstract: In a clock generating circuit, clocks generated therein are distributed by a clock distribution control circuit for every circuit block. In a clock output control circuit, a clock command is decoded by a clock command decoder and output of the clocks is controlled for every circuit block. A data transfer control device having a clock control circuit functions as a first device or a second device to transfer data as a host or a peripheral. When the data transfer control device function as a second device and in an idle state, it controls clock output to a state controller which controls switching between a host function and a peripheral function.

Abstract: A transaction is automatically issued with respect to one of end points and data is automatically transferred while the remaining data size of the transfer data is calculated based on the total size and the maximum packet size. When the remaining data size in the current transaction is less than the maximum packet size, the next transaction is issued automatically, and a short packet is transferred automatically to nest one of the end points. When the payload size of the packet to be transferred by the current transaction is the maximum packet size and the remaining data size of the transfer data is zero, a short packet of zero data length is transferred automatically to the next one of the end points. When DMA transfer is complete and the remaining data to be transferred is zero, a short packet of zero data length is transferred automatically in response to an IN token from a host. Data transfer according to USB On-The-Go is performed.

Abstract: An oscillation circuit generates a reference clock signal for a clock signal supplied to each section of a data transfer control device. In a clock output control circuit, a clock command is decoded by a clock command decoder and oscillation of the oscillation circuit is controlled. The data transfer control device including a clock control circuit transfers data as a host or a peripheral in a state being set to either a self-powered first device or a second device which can operate by using a power supply on a bus. The oscillation operation of the oscillation circuit is suspended in an idle state of the second device.

Abstract: A plurality of pipe regions PIPE0 to PIPEe in which data transferred to and from endpoints is stored are allocated in a packet buffer (FIFO). Transfer condition information on data transfer between the pipe regions and the endpoints is set in transfer condition registers TREG0 to TREGe in a register section. A host (transfer) controller automatically generates a transaction for each of the endpoints based on the transfer condition information (total size, maximum packet size, transfer direction, number of continuous execution times, token issue interval, and the like) set in the transfer condition registers, and automatically transfers data between each pipe region and the endpoint. An OTG (state) controller which controls a state of USB On-The-Go is provided. The pipe regions are allocated in the packet buffer during a host operation.

Abstract: A data transfer control device includes an OTG (state) controller which controls a plurality of states including a host operation state and a peripheral operation state, a host controller which is connected with a transceiver during the host operation, a peripheral controller which is connected with the transceiver during the peripheral operation, a register section including transfer condition registers which are used commonly during the host operation and the peripheral operation, and a buffer controller which controls access to a packet buffer used commonly by the host controller and the peripheral controller. Pipe regions PIPE0 to PIPEe are allocated in the packet buffer during the host operation, and endpoint regions EP0 to EPe are allocated in the packet buffer during the peripheral operation.

Abstract: The adsorbent for separation and recovery of CO is prepared by contacting an alumina or silica-alumina carrier with a mixed solution or dispersion of a cupric salt and a reducing agent in a solvent and, then, removing the solvent. The preferred cupric salt is cupric chloride.