Patents by Inventor Hiroaki Ueno

Hiroaki Ueno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070210332
    Abstract: It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform.
    Type: Application
    Filed: March 2, 2007
    Publication date: September 13, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hiroaki UENO, Tetsuzo Ueda, Yasuhiro Uemoto, Daisuke Ueda, Tsuyoshi Tanaka, Manabu Yanagihara, Yutaka Hirose, Masahiro Hikita
  • Publication number: 20070170463
    Abstract: A nitride semiconductor device includes: a first semiconductor layer made of first nitride semiconductor; a second semiconductor layer formed on a principal surface of the first semiconductor layer and made of second nitride semiconductor having a bandgap wider than that of the first nitride semiconductor; a control layer selectively formed on, or above, an upper portion of the second semiconductor layer and made of third nitride semiconductor having a p-type conductivity; source and drain electrodes formed on the second semiconductor layer at respective sides of the control layer; a gate electrode formed on the control layer; and a fourth semiconductor layer formed on a surface of the first semiconductor layer opposite to the principal surface, having a potential barrier in a valence band with respect to the first nitride semiconductor and made of fourth nitride semiconductor containing aluminum.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 26, 2007
    Inventors: Hiroaki Ueno, Manabu Yanagihara, Tetsuzo Ueda, Yasuhiro Uemoto, Tsuyoshi Tanaka, Daisuke Ueda
  • Patent number: 7248424
    Abstract: A nonlinearity measuring method capable of measuring NLTS with a higher precision while taking the state of magnetization inversion of a preceding bit string into consideration. A constitution includes a first measuring section measuring a first predetermined higher harmonic component from a regenerated signal of the reference signal magnetically recorded on a medium, a second measuring section measuring a second predetermined higher harmonic component from regenerated signals with respect to plural kinds of signals to be measured magnetically recorded on the medium, and a calculating section calculating NLTS from the first component and the second component corresponding to each of the signals, wherein each of plural kinds of signals to be measured includes a magnetization inversion pattern string P1 preceding the objective bit to be measured of NLTS; thereby NLTS depending on the string P1 can be quantitatively measured easily.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: July 24, 2007
    Assignee: Fujitsu Limited
    Inventor: Hiroaki Ueno
  • Publication number: 20070126115
    Abstract: A package substrate has a substrate body on which an electronic component is mounted. The substrate body is formed at its top or back surface with a diamond film, a diamond-like carbon film or a carbon film.
    Type: Application
    Filed: November 7, 2006
    Publication date: June 7, 2007
    Inventors: Manabu Yanagihara, Hiroaki Ueno, Yasuhiro Uemoto, Tsuyoshi Tanaka
  • Publication number: 20070126026
    Abstract: A semiconductor device includes: a first group-III nitride semiconductor layer formed on a substrate; a second group-III nitride semiconductor layer made of a single layer or two or more layers, formed on the first group-III nitride semiconductor layer, and acting as a barrier layer; a source electrode, a drain electrode, and a gate electrode formed on the second group-III nitride semiconductor layer, the gate electrode controlling a current flowing between the source and drain electrodes; and a heat radiation film with high thermal conductivity which covers, as a surface passivation film, the entire surface other than a bonding pad.
    Type: Application
    Filed: November 6, 2006
    Publication date: June 7, 2007
    Inventors: Hiroaki Ueno, Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka
  • Patent number: 7217960
    Abstract: It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform.
    Type: Grant
    Filed: January 5, 2006
    Date of Patent: May 15, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Ueno, Tetsuzo Ueda, Yasuhiro Uemoto, Daisuke Ueda, Tsuyoshi Tanaka, Manabu Yanagihara, Yutaka Hirose, Masahiro Hikita
  • Patent number: 7213218
    Abstract: A semiconductor device simulation method includes the step of storing, in a storage unit, a surface potential and threshold voltage obtained by computation, the step of computing thermal drain noise on the basis of the data of the surface potential and thermal drain noise stored in the storage unit, and the step of determining whether or not to reduce thermal drain noise, and reflecting the computation result in simulation of the model when it is determined that thermal drain noise is to be reduced. A drain current Ids of a MOSFET is calculated and substituted into a relational expression for a drain current noise spectrum density obtained from a Nyquist theorem equation, thereby calculating a thermal drain noise coefficient ? of the MOSFET by substituting the current Ids into a relational expression for a thermal drain noise spectrum density which is obtained from the Nyquist logical equation.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: May 1, 2007
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Mitiko Miura, Hiroaki Ueno, Satoshi Hosokawa
  • Publication number: 20070012415
    Abstract: Disclosed is an apparatus for and a method of thixocasting a cast iron, that can effectively prevent the scale from mixing in the die (cavity) thereby to obtain sound iron castings having good mechanical properties. The apparatus includes at least a pair of dies that can freely opened and closed to define a cavity to be filled under a pressure, and an injector that injects the semi-molten iron into the cavity through a hole in a gate at the entry of the cavity so as to throttle the entry. The gate is a separate member disposed at the entry of the cavity every time an injection casting operation is carried out and is taken out together with the casting after the injection casting operation.
    Type: Application
    Filed: August 24, 2004
    Publication date: January 18, 2007
    Inventors: Masayuki Tsuchiya, Hiroaki Ueno, Chiaki Ushigome, Toshiro Maekawa, Syuichi Shikai
  • Patent number: 7142380
    Abstract: Data is read out from a disk in which the data is recorded in the perpendicular magnetic recording system by a head, amplified by a head preamplifier, and signal-processed by a read channel LSI. A read-out processing unit of a HDD controller sends out signals processed by the read channel LSI as an output of the perpendicular magnetic recording system. Further, a cut-off frequency controlling unit of the HDD controller determines a cut-off frequency of a high-pass filter of the head preamplifier based on a data transfer rate read out by the read-out processing unit, controls a cut-off frequency changing unit, and changes the value of the cut-off frequency.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: November 28, 2006
    Assignee: Fujitsu Limited
    Inventor: Hiroaki Ueno
  • Publication number: 20060221476
    Abstract: In the case that perpendicular magnetic recording is used, when a cut-off frequency fc of a high-pass filter of a head output is small, an error rate can be improved more when a PR target having a DC component is used and, when the cut-off frequency fc is large, an error rate can be improved more when a PR target not having a DC component is used. With this fact as a logical ground, in the present invention, when TA does not occur, PR equalization is performed using the PR target having a DC component and, when TA occurs, the cut-off frequency fc is increased to cut a low frequency component of a head reproduction signal and, additionally, PR equalization is performed using the PR target not having a DC component.
    Type: Application
    Filed: July 27, 2005
    Publication date: October 5, 2006
    Inventor: Hiroaki Ueno
  • Publication number: 20060157729
    Abstract: It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform.
    Type: Application
    Filed: January 5, 2006
    Publication date: July 20, 2006
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hiroaki Ueno, Tetsuzo Ueda, Yasuhiro Uemoto, Daisuke Ueda, Tsuyoshi Tanaka, Manabu Yanagihara, Yutaka Hirose, Masahiro Hikita
  • Publication number: 20060149075
    Abstract: The invention relates to type A crystal of 5-[{6-(2-fluorobenzyl)oxy-2-naphtyl}methyl]-2,4-thiazolidinedione characterized to have characteristic absorption peaks (2?) at 11.5°±0.3°, 14.5°±0.2°, 16.2°±0.3°, 17.0°±0.3°, 17.7°±0.2°, 18.6°±0.3°, 19.1°±0.2°, 21.3°±0.4°, 22.4°±0.5°, 25.7°±1.5° and 28.3°±10.5° in a powder X-ray diffraction pattern, and also to a method for preparation thereof, and a pharmaceutical composition comprising the same. The crystal is excellent in stability, and has advantages in handling, storage, and pharmaceutical preparation. The invention also relates to type B, C and D crystals of said compound.
    Type: Application
    Filed: February 21, 2006
    Publication date: July 6, 2006
    Inventors: Takayuki Oe, Hiroaki Ueno, Akira Maruyama, Katsuhiko Masuda
  • Publication number: 20060060895
    Abstract: In the structure of a semiconductor device of the present invention, a first source electrode is connected to a conductive substrate through a via hole, and a second source electrode is formed. Thus, even if a high reverse voltage is applied between a gate electrode and a drain electrode, electric field concentration likely to occur at an edge of the gate electrode closer to the drain electrode can be effectively dispersed or relaxed. Moreover, the conductive substrate is used as a substrate for forming element formation layers, so that a via hole penetrating the substrate to reach the backside thereof does not have to be formed in the conductive substrate. Thus, with the strength necessary for the conductive substrate maintained, the first source electrode can be electrically connected to a backside electrode.
    Type: Application
    Filed: August 1, 2005
    Publication date: March 23, 2006
    Inventors: Masahiro Hikita, Hiroaki Ueno, Yutaka Hirose, Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka
  • Publication number: 20060056089
    Abstract: Data is read out from a disk in which the data is recorded in the perpendicular magnetic recording system by a head, amplified by a head preamplifier, and signal-processed by a read channel LSI. A read-out processing unit of a HDD controller sends out signals processed by the read channel LSI as an output of the perpendicular magnetic recording system. Further, a cut-off frequency controlling unit of the HDD controller determines a cut-off frequency of a high-pass filter of the head preamplifier based on a data transfer rate read out by the read-out processing unit, controls a cut-off frequency changing unit, and changes the value of the cut-off frequency.
    Type: Application
    Filed: January 24, 2005
    Publication date: March 16, 2006
    Inventor: Hiroaki Ueno
  • Publication number: 20050190471
    Abstract: A nonlinearity measuring method capable of measuring NLTS with a higher precision while taking the state of magnetization inversion of a preceding bit string into consideration. A constitution includes a first measuring section measuring a first predetermined higher harmonic component from a regenerated signal of the reference signal magnetically recorded on a medium, a second measuring section measuring a second predetermined higher harmonic component from regenerated signals with respect to plural kinds of signals to be measured magnetically recorded on the medium, and a calculating section calculating NLTS from the first component and the second component corresponding to each of the signals, wherein each of plural kinds of signals to be measured includes a magnetization inversion pattern string P1 preceding the objective bit to be measured of NLTS; thereby NLTS depending on the string P1 can be quantitatively measured easily.
    Type: Application
    Filed: May 2, 2005
    Publication date: September 1, 2005
    Inventor: Hiroaki Ueno
  • Patent number: 6934100
    Abstract: Method of accurately measuring various kinds of non-linear transition shifts (NLTSs) in the magnetic recording/reproduction using an MR-type reproducing head is provided. According to the method, the data of a reference bit-string pattern are sent, as reference signals, to a magnetic disk 2 via a head IC 5 and a magnetic head 3 so as to be magnetically recorded. A first predetermined harmonic component Vnref is measured from the reproduced signals of the record data detected by the magnetic head 3, a bit-string pattern is selected from plural kinds of predetermined bit-string patterns, the data of the selected bit-string pattern are sent, as to-be-measured signals, to the magnetic disk 2, a second predetermined harmonic component Vnpat is measured from the reproduced signals, and the NLTS is calculated from Vnref and Vnpat.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: August 23, 2005
    Assignee: Fujitsu Limited
    Inventor: Hiroaki Ueno
  • Patent number: 6923246
    Abstract: A billet for a thixocasting process and a thixocasting process using the billet allows casting using a thixocasting process to be realized at low production cost without permeation of an oxide film to the inside of the billet in injection molding. In a billet used for a thixocasting process continuously cast by intermittently drawing out, the interval of the oscillation marks is 10 mm or less and the maximum tilt angle of the oscillation marks relative to a cross section which is at a right angle to the drawing out direction is 45° or less.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: August 2, 2005
    Assignees: Honda Giken Kogyo Kabushiki Kaisha, Kogi Corporation
    Inventors: Masayuki Tsuchiya, Hiroaki Ueno, Yasushi Fujinaga, Chiaki Ushigome, Susumu Nishikawa
  • Publication number: 20050155004
    Abstract: A semiconductor device simulation method includes the step of storing, in a storage unit, a surface potential and threshold voltage obtained by computation, the step of computing thermal drain noise on the basis of the data of the surface potential and thermal drain noise stored in the storage unit, and the step of determining whether or not to reduce thermal drain noise, and reflecting the computation result in simulation of the model when it is determined that thermal drain noise is to be reduced. A drain current Ids of a MOSFET is calculated and substituted into a relational expression for a drain current noise spectrum density obtained from a Nyquist theorem equation, thereby calculating a thermal drain noise coefficient ? of the MOSFET by substituting the current Ids into a relational expression for a thermal drain noise spectrum density which is obtained from the Nyquist logical equation.
    Type: Application
    Filed: December 13, 2004
    Publication date: July 14, 2005
    Inventors: Mitiko Miura, Hiroaki Ueno, Satoshi Hosokawa
  • Publication number: 20050111593
    Abstract: A reproducing apparatus comprising a reproducing head for reproducing encoded data from a recording medium, an internal code APP circuit for decoding an internal code of the encoded data, and an external code APP circuit for decoding an external code and outputting the result as preliminary information of the internal code, further comprises a ? setting circuit for setting a ? value to the internal code APP circuit, and an error rate calculating circuit for calculating an error rate. The ? setting circuit varies the ? value. The error rate calculating circuit calculates the error rate of each ? value. Based on the error rate, the ? setting circuit determines the ? value at which good error rate is provided as the optimal ? value, and sets it to the internal code APP circuit.
    Type: Application
    Filed: December 22, 2004
    Publication date: May 26, 2005
    Inventor: Hiroaki Ueno
  • Patent number: 6863744
    Abstract: An iron based alloy material for a thixocasting process and a method for casting the material which extends the service life of dies by inhibiting solidification contraction, and in which casting defects such as size variations and cracks can be inhibited. The material comprises 1.6 wt %?C?2.5 wt % and 3.0 wt %<Si?5.5 wt %, and a carbon equivalent (the value of CE) defined as “C(wt %)+?Si(wt %)” of 2.9 to 3.5. This material is made to be in a half-melted state with 35 to 50 wt % of a solid phase to be cast under a pressure load.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: March 8, 2005
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Masayuki Tsuchiya, Hiroaki Ueno