Patents by Inventor Hiroaki Yokoyama

Hiroaki Yokoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020109195
    Abstract: A semiconductor device, such as a BiCMOS, includes a bipolar transistor having at least an emitter region. An emitter electrode is formed on the emitter region. Further, a wiring pattern is formed over the emitter region. A plurality of contact plugs are formed to electrically connect the emitter electrode with the wiring pattern. The contact plugs are partially embedded in the emitter electrode in order to prevent of reduction of the current amplification factor of the bipolar transistor.
    Type: Application
    Filed: April 30, 2002
    Publication date: August 15, 2002
    Applicant: NEC CORPORATION
    Inventor: Hiroaki Yokoyama
  • Publication number: 20020074540
    Abstract: In a semiconductor device including a large-diameter contact hole and a small-diameter contact hole which are formed to penetrate through an insulator film formed on a semiconductor substrate, the small-diameter contact hole is completely filled with a refractory conductive material, and the large-diameter contact hole has a sidewall formed of the refractory conductive material on a side surface of the large-diameter contact hole. The sidewall covers the side surface lower than a position which is lower than an upper end of the large-diameter contact hole by a predetermined distance.
    Type: Application
    Filed: December 17, 1997
    Publication date: June 20, 2002
    Inventor: HIROAKI YOKOYAMA
  • Patent number: 6396110
    Abstract: A semiconductor device, such as a BiCMOS, includes a bipolar transistor having at least an emitter region. An emitter electrode is formed on the emitter region. Further, a wiring pattern is formed over the emitter region. A plurality of contact plugs are formed to electrically connect the emitter electrode with the wiring pattern. The contact plugs are partially embedded in the emitter electrode in order to prevent of reduction of the current amplification factor of the bipolar transistor.
    Type: Grant
    Filed: February 28, 2000
    Date of Patent: May 28, 2002
    Assignee: NEC Corporation
    Inventor: Hiroaki Yokoyama
  • Publication number: 20010029079
    Abstract: A semiconductor device, such as a BICMOS, includes a bipolar transistor having at least an emitter region. An emitter electrode is formed on the emitter region. Further, a wiring pattern is formed over the emitter region. A plurality of contact plugs are formed to electrically connect the emitter electrode with the wiring pattern. The contact plugs are partially embedded in the emitter electrode in order to prevent of reduction of the current amplification factor of the bipolar transistor.
    Type: Application
    Filed: April 25, 2001
    Publication date: October 11, 2001
    Applicant: NEC Corporation
    Inventor: Hiroaki Yokoyama
  • Publication number: 20010017132
    Abstract: A burner case (14) has at least one burner (11) therein and has an upper surface (12) formed with at least one opening (13). A flame produced by the burner (11) is introduced externally through the opening (13) for heating an object put on the upper surface (12) of the burner case (14). The upper surface (12) of the burner case (14) is formed along the opening (13) with an upwardly projecting louver (15). The louver acts as a windshield for the flame. For instance, the opening (13) is an annular opening, and the louver (15) is formed in inclination along the annular opening at an outer edge of the annular opening.
    Type: Application
    Filed: December 18, 2000
    Publication date: August 30, 2001
    Inventors: Hiroaki Yokoyama, Toshiaki Abe, Hideki Azeyagi
  • Patent number: 6225179
    Abstract: A bi-MOS circuit is fabricated on first active regions assigned to the bipolar transistor and on second active regions assigned to the field effect transistors, and the field effect transistors are fabricated after said bipolar transistor, because a high-temperature heat treatment for an emitter diffusion destroys the impurity profiles of the source/drain regions of the field effect transistors, wherein a part of the field oxide layer between the second active regions is covered with an etching stopper layer before deposition of a thick silicon oxide layer in order to widely space the emitter region from the emitter electrode, even though the thick silicon oxide layer is removed from the field oxide layer between the second active regions for fabricating the field effect transistors, the etching stopper layer prevents the field oxide layer from the etchant, and the field oxide layer between the second active regions maintains the original thickness, thereby never allowing a parasitic MOS transistor to turn on
    Type: Grant
    Filed: March 2, 1999
    Date of Patent: May 1, 2001
    Assignee: NEC Corporation
    Inventor: Hiroaki Yokoyama
  • Patent number: 6213760
    Abstract: There is provided a burner to be used for a portable gas cooking stove, including (a) a mixture gas pipe having an open end through which a gas mixture of combustible gas and air is exhausted, (b) a burner head connected to the mixture gas pipe in a hermetically sealed condition and having at least one opening at a surface thereof, the gas mixture blowing out through the opening, and (c) an igniter igniting the gas mixture blowing out through the opening of the burner head, the igniter generating a spark in a direction perpendicular to a flow of the gas mixture blowing out through the opening of the burner head. The burner makes it possible for the spark to make contact with the gas mixture flow in a larger contact area than that of a conventional burner. Accordingly, it is possible to stably ignite the gas mixture, even if the gas mixture has a great flow velocity.
    Type: Grant
    Filed: January 5, 2000
    Date of Patent: April 10, 2001
    Assignee: Snow Peak, Inc.
    Inventor: Hiroaki Yokoyama
  • Patent number: 6173709
    Abstract: There is provided a portable gas cooking stove, including (a) a mixture gas pipe having an open end through which a mixture gas of combustible gas and air is exhausted, (b) a burner head connected to the mixture gas pipe in a hermetically sealed condition and having at least one opening at a surface thereof, the mixture gas blowing out through the opening, (c) an igniter igniting the mixture gas blowing out through the opening of the burner head, and (d) a windscreen surrounding the burner head and formed with a flame hole facing the opening of the burner head, the igniter being located outside the windscreen in facing relation to the flame hole. The portable gas cooking stove makes it no longer necessary to provide a net to an inner wall of a burner head, which was necessary to do in a conventional gas cooking stove, ensuring reduction in a period of time necessary for fabricating a flame hole and simplification in steps of fabricating a flame hole.
    Type: Grant
    Filed: January 13, 2000
    Date of Patent: January 16, 2001
    Assignee: Snow Peak, Inc.
    Inventor: Hiroaki Yokoyama
  • Patent number: 6070989
    Abstract: There is provided a globe supporting structure that supports a globe of a gas lantern which burns combustible gas discharged from a gas cartridge containing the combustible gas by means of a burner head located inside the globe, including a ventilator positioned above the globe, a plurality of wires rotatably arranged on the ventilator, each of which rotates about the ventilator, and is shaped so as to be capable of reaching a bottom surface of the globe, and a globe supporting plate that supports the globe, and is provided with first arrangement which is detachably engagable with a portion of the wires reaching the bottom surface of the globe. In accordance with the globe supporting structure, the globe can be removed easily from the globe supporting plate without breaking the globe.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: June 6, 2000
    Assignee: Snow Peak, Inc.
    Inventors: Hiroaki Yokoyama, Toshikazu Ikarashi
  • Patent number: 6066521
    Abstract: In a method for manufacturing a BiMOS device, first and second semiconductor layers are formed on a semiconductor substrate, first and second field insulating layers are formed by using a LOCOS process on said first and second semiconductor layers, respectively. The first field insulating layer partitions a bipolar transistor area and a MOS transistor area, and the second field insulating layer is formed on a base-emitter junction region of the first semiconductor layer. Then, impurities are introduced via the second field insulating layer into the first semiconductor layer to form a base region therein. Then, an emitter opening is perforated in the second field insulating layer, and a polycrystalline silicon layer is formed on the second field insulating layer. Then, impurities of a first conductivity type are introduced into the polycrystalline silicon layer, and a heating operation is performed upon the polycrystalline silicon layer to form an emitter region.
    Type: Grant
    Filed: February 24, 1999
    Date of Patent: May 23, 2000
    Assignee: NEC Corporation
    Inventors: Hiroaki Yokoyama, Toshio Komuro
  • Patent number: 6022780
    Abstract: A side wall spacer and a spacer layer are concurrently formed from an insulating layer in such a manner that the side wall spacer is on one side surface of a gate electrode and the spacer layer covers a drain forming area and the other side surface of the gate electrode, and n-type dopant impurity is ion implanted into the drain forming area and a source forming area, thereby concurrently forming a shallow drain region and a deep source region on both sides of the gate electrode.
    Type: Grant
    Filed: August 13, 1998
    Date of Patent: February 8, 2000
    Assignee: NEC Corporation
    Inventor: Hiroaki Yokoyama
  • Patent number: 5957683
    Abstract: There is provided a burner structure used for a portable gas cooking stove, including a mixing tube with an open end from which a mixture gas of a combustible gas and air is discharged, a burner head with a predetermined volume, an open bottom surface, and a top surface with at least one opening, an inner cup having a size that enables the inner cup to be housed in the burner head, and an open bottom surface, and a bottom plate with a through-hole through which the mixing tube can be inserted, covering the open bottom surface of the burner head, wherein the inner cup is installed inside the burner head in such a manner that an inner surface of the inner cup faces the mixing tube, and the mixing tube is installed on the bottom plate so that the open end is positioned higher than a bottom surface of the inner cup.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: September 28, 1999
    Assignee: Snow Peak, Inc.
    Inventors: Hiroaki Yokoyama, Toshikazu Ikarashi
  • Patent number: 5933720
    Abstract: In a method for manufacturing a BiMOS device, first and second semiconductor layers are formed on a semiconductor substrate, first and second field insulating layers are formed by using a LOCOS process on said first and second semiconductor layers, respectively. The first field insulating layer partitions a bipolar transistor area and a MOS transistor area, and the second field insulating layer is formed on a base-emitter junction region of the first semiconductor layer. Then, impurities are introduced via the second field insulating layer into the first semiconductor layer to form a base region therein. Then, an emitter opening is perforated in the second field insulating layer, and a polycrystalline silicon layer is formed on the second field insulating layer. Then, impurities of a first conductivity type are introduced into the polycrystalline silicon layer, and a heating operation is performed upon the polycrystalline silicon layer to form an emitter region.
    Type: Grant
    Filed: April 25, 1997
    Date of Patent: August 3, 1999
    Assignee: NEC Corporation
    Inventors: Hiroaki Yokoyama, Toshio Komuro
  • Patent number: 5598013
    Abstract: A semiconductor device according to the invention includes a first conductivity type of driver transistor, a second conductivity type of load transistor formed on the driver transistor and an insulation layer formed between the driver transistor and the load transistor. The insulation layer is provided thereon with a depression area in which a channel region, a gate insulation layer and a gate electrode of the load transistor are formed.
    Type: Grant
    Filed: December 5, 1994
    Date of Patent: January 28, 1997
    Assignee: NEC Corporation
    Inventor: Hiroaki Yokoyama
  • Patent number: 5482889
    Abstract: A method for the preparation of semiconductor devices which comprises steps of forming a nitride film on a first conductivity type semiconductor substrate, selectively removing the nitride film, oxidation with the remaining nitride film as the mask to form insulation oxide films for element isolation on the semiconductor substrate, forming a second insulation film on the entire surface of the substrate, and implanting a second conductivity type impurity through the entire surface of the substrate to form second conductivity type channel stoppers under the insulation oxide films.
    Type: Grant
    Filed: April 19, 1995
    Date of Patent: January 9, 1996
    Assignee: NEC Corporation
    Inventor: Hiroaki Yokoyama