Abstract: A semiconductor device includes a plurality of gate electrodes, source and drain regions, a plurality of source contacts, a plurality of drain contacts, substrate contacts, and a salicide block. The gate electrodes are arrayed in parallel on a semiconductor region on a semiconductor substrate. The source and drain regions are formed in the semiconductor region on both sides of each gate electrode. The source contacts are formed on the source region. The drain contacts are formed on the drain region. The substrate contacts are formed on the semiconductor substrate and electrically connect to the semiconductor substrate. The salicide block is formed between the gate electrode and the plurality of drain contacts. The salicide block prevents silicidation on the drain region. The length of the salicide block in a channel length direction increases as the distance from the substrate contact increases.

Abstract: A semiconductor device includes a plurality of gate electrodes, source and drain regions, a plurality of source contacts, a plurality of drain contacts, substrate contacts, and a salicide block. The gate electrodes are arrayed in parallel on a semiconductor region on a semiconductor substrate. The source and drain regions are formed in the semiconductor region on both sides of each gate electrode. The source contacts are formed on the source region. The drain contacts are formed on the drain region. The substrate contacts are formed on the semiconductor substrate and electrically connect to the semiconductor substrate. The salicide block is formed between the gate electrode and the plurality of drain contacts. The salicide block prevents silicidation on the drain region. The length of the salicide block in a channel length direction increases as the distance from the substrate contact increases.

Abstract: An ESD protection device comprising a field-effect transistor which including a source/drain diffusion layer formed in a semiconductor region, a gate insulating film formed on a channel region between the source/drain diffusion layers, and a gate electrode formed on the gate insulating film. The first silicide layer formed on a region of one portion of the source/drain diffusion layer. A diffusion layer formed in the semiconductor region of a non-forming region of the first silicide layer in the source/drain diffusion layer. A junction depth of the diffusion layer is smaller than that of the source/drain diffusion layer.