Abstract: A current limiting circuit is used in a display device which includes a display panel having pixels each of which includes a light emitting element and a panel power source which supplies an application voltage to be applied to each of the light emitting elements included in the pixels. The current limiting circuit detects a supply current supplied from the panel power source to the display panel, and reduces the application voltage when a value of the supply current detected is greater than a threshold.

Abstract: A printed board has an elongated shape and is to be electrically coupled to a display panel via a flexible board. The printed board includes a first board section; and a second board section shorter in length than the first board section in a substantially perpendicular direction to a longitudinal direction of the printed board. The first board section and the second board section are disposed in a row in the longitudinal direction, each of the first board section and the second board section has a first end in the substantially perpendicular direction to the longitudinal direction, the first end of the first board section projects further than the first end of the second board section in the substantially perpendicular direction, and a connection portion to be connected to the flexible board is disposed at the first end of each of the first board section and the second board section.

Abstract: A printed board has an elongated shape and is to be electrically coupled to a display panel via a flexible board. The printed board includes a first board section; and a second board section shorter in length than the first board section in a substantially perpendicular direction to a longitudinal direction of the printed board. The first board section and the second board section are disposed in a row in the longitudinal direction, each of the first board section and the second board section has a first end in the substantially perpendicular direction to the longitudinal direction, the first end of the first board section projects further than the first end of the second board section in the substantially perpendicular direction, and a connection portion to be connected to the flexible board is disposed at the first end of each of the first board section and the second board section.

Abstract: A current limiting circuit is used in a display device which includes a display panel having pixels each of which includes a light emitting element and a panel power source which supplies an application voltage to be applied to each of the light emitting elements included in the pixels. The current limiting circuit detects a supply current supplied from the panel power source to the display panel, and reduces the application voltage when a value of the supply current detected is greater than a threshold.

Abstract: In a semiconductor integrated circuit chip including an interconnect layer in which there is a limitation on the lengths of interconnects or areas occupied by the interconnects, empty spaces between power supply interconnect segments having the same potential located in parallel to a priority interconnect direction, are shifted relative to each other within the limits of the lengths and areas of power supply interconnects. As a result, a local increase in resistance is dispersed, whereby an influence on a voltage drop is reduced.

Abstract: In a semiconductor integrated circuit chip including an interconnect layer in which there is a limitation on the lengths of interconnects or areas occupied by the interconnects, empty spaces between power supply interconnect segments having the same potential located in parallel to a priority interconnect direction, are shifted relative to each other within the limits of the lengths and areas of power supply interconnects. As a result, a local increase in resistance is dispersed, whereby an influence on a voltage drop is reduced.

Abstract: A method for designing an interconnect structure of an interconnect layer in a semiconductor integrated circuit device includes the steps of: (a) inputting layout data of the semiconductor integrated circuit device; (b) controlling an air gap exclusion area based interconnects in the layout data; and (c) outputting layout data including the air gap exclusion area determined in the step (b).

Abstract: Circuit data on a semiconductor integrated circuit, design constraints as to design of the semiconductor integrated circuit, air gap information on air gap creation in the circuit data, and an air gap volume constraint specifying an allowable range for an air gap volume value are received. The sum total of the values of the volumes of air gaps created in the circuit data according to the air gap information is calculated. Upon detection that the calculated sum total of the air gap volume values falls outside the allowable range specified by the air gap volume constraint, the circuit data is optimized so that the design constraints are satisfied and the sum total of the air gap volume values falls within the allowable range.

Abstract: Circuit data on a semiconductor integrated circuit, design constraints as to design of the semiconductor integrated circuit, air gap information on air gap creation in the circuit data, and an air gap volume constraint specifying an allowable range for an air gap volume value are received. The sum total of the values of the volumes of air gaps created in the circuit data according to the air gap information is calculated. Upon detection that the calculated sum total of the air gap volume values falls outside the allowable range specified by the air gap volume constraint, the circuit data is optimized so that the design constraints are satisfied and the sum total of the air gap volume values falls within the allowable range.

Abstract: A method for designing an interconnect structure of an interconnect layer in a semiconductor integrated circuit device includes the steps of: (a) inputting layout data of the semiconductor integrated circuit device; (b) controlling an air gap exclusion area based interconnects in the layout data; and (c) outputting layout data including the air gap exclusion area determined in the step (b).