Abstract: A parity generating circuit in a 0 side receives input signals on respective signal lines and produces a parity bit based on the input signals. A parallel/serial converting circuit multiplexes parallel signals (or input signals) and the parity bit into a serial signal with reference to a timing signal. A serial/parallel converting circuit in a 1 side reproduces parallel signals and a parity signal and produces a parity check timing signal. A parity checking circuit checks a parity of the parallel signals by the use of the parity signal. If normal, a state holding circuit holds outputs of the parity checking circuit as a state signal. If abnormal, held content of the state holding circuit is cleared.

Abstract: A high-performance and miniaturizable duplexed processor system is provided. In communications between respective corresponding processor units on 0- and 1-system processor cards C0 and C1, a sequence number is added to transmission data to assess the continuity of the transmission data, and to thereby retransmit missing data. Also, in communications between processor units on the same processor card, interprocessor connection units PC0 and PC1 autonomously transfer data. Furthermore, each processor card is equipped with an input/output unit (an input/output switching unit and an input/output interface unit), so that each input/output switching unit IC0 and IC1 switches input data paths according to operating states of the processor card equipped therewith.

Abstract: A parity generating circuit in a 0 side receives input signals on respective signal lines and produces a parity bit based on the input signals. A parallel/serial converting circuit multiplexes parallel signals (or input signals) and the parity bit into a serial signal with reference to a timing signal. A serial/parallel converting circuit in a 1 side reproduces parallel signals and a parity signal and produces a parity check timing signal. A parity checking circuit checks a parity of the parallel signals by the use of the parity signal. If normal, a state holding circuit holds outputs of the parity checking circuit as a state signal. If abnormal, held content of the state holding circuit is cleared.

Abstract: A parity generating circuit in a 0 side receives input signals on respective signal lines and produces a parity bit based on the input signals. A parallel/serial converting circuit multiplexes parallel signals (or input signals) and the parity bit into a serial signal with reference to a timing signal. A serial/parallel converting circuit in a 1 side reproduces parallel signals and a parity signal and produces a parity check timing signal. A parity checking circuit checks a parity of the parallel signals by the use of the parity signal. If normal, a state holding circuit holds outputs of the parity checking circuit as a state signal. If abnormal, held content of the state holding circuit is cleared.

Abstract: A high-performance and miniaturizable duplexed processor system is provided. In communications between respective corresponding processor units on 0- and 1-system processor cards C0 and C1, a sequence number is added to transmission data to assess the continuity of the transmission data, and to thereby retransmit missing data. Also, in communications between processor units on the same processor card, interprocessor connection units PC0 and PC1 autonomously transfer data. Furthermore, each processor card is equipped with an input/output unit (an input/output switching unit and an input/output interface unit), so that each input/output switching unit IC0 and IC1 switches input data paths according to operating states of the processor card equipped therewith.

Abstract: A parity generating circuit 201 in a 0 side 20 receives input signals s21 on respective signal lines and produces a parity bit p20 based on the input signals s21. A parallel/serial converting circuit 203 multiplexes parallel signals s22 (or input signals s21) and the parity bit p20 into a serial signal s23 with reference to a timing signal t20. A serial/parallel converting circuit 211 in a 1 side 21 is reproduces parallel signals S24 and a parity signal p21 and produces a parity check timing signal t21. A parity checking circuit 212 checks a parity of the parallel signals s24 by the use of the parity signal p21. If normal, a state holding circuit 213 holds outputs s25 of the parity checking circuit 212 as a state signal. If abnormal, held content of the state holding circuit 213 is cleared.

Abstract: A micro processor board of the bus control system comprises an internal bus which address lines, data lines, and control signal lines. The micro processor board also includes a memory connected via the internal bus with the micro processor, registers such as a system control register, and a bus interface circuit. Access to the main memory, the register, or the bus interface which is executed by the micro processor is outputted from an external bus via the bus interface circuit. Thus, the operational status of the micro processor or the internal bus can be traced by tracing the external bus.

Abstract: A connector includes a connector housing and a plurality of contacts. Each of the plurality of contacts is composed of a contact section for contacting another contact, a lead section to be connected with a conductor, and a connecting section for connecting the contact section and the lead section. The lead section is composed of a bent portion and a flat portion provided substantially outside of said connector housing.

Abstract: A micro processor board of the bus control system comprises an internal bus which comprise a micro processor, address lines, data lines, and control signal lines, a memory connected via the internal bus with the micro processor, registers such as a system control register, and a bus interface circuit. The access to the main memory, the register, or the bus interface which is executed by the micro processor is outputted from an external bus via the bus interface circuit. Thus, the operation status of the micro processor or the internal bus can be traced by tracing the external bus.

Abstract: In an information processing system comprising an input/output device, a main memory device, a processing device including a first-in first-out type write-in buffer, and a bus connecting thereamong, the first-in first-out type write-in buffer comprises a flag bit holding area for holding a bus release request signal from the input/output device as a flag bit to produce the flag bit as a flag signal. The bus arbitration circuit determines the bus available right so as to grant a priority right for data write-in processing by the input/output device rather than data write-in processing by the processing device when the bus arbitration circuit receives the flag signal. The bus arbitration circuit determines the bus available right on the basis of the bus release request and the flag signal.