Abstract: A semiconductor integrated circuit includes a plurality of functional blocks placed on a semiconductor chip and being respectively provided with predetermined functions by semiconductor devices and a gate array block placed on said chip. The gate array block includes a plurality of electrically connected basic cells implementing desired functions. The gate array block has a circuit designed after placing the functional blocks and the basic cells on the chip. The functional blocks and gate array block are laid out with at least one common mask in a first area including a center position on a surface of the semiconductor chip. The circuit also includes I/O buffers surrounding the first area.

Abstract: An IC chip comprises a chip peripheral portion and a core macro portion. The chip peripheral portion is made up of a plurality of I/O buffers each of which serves as an interface between the IC chip and the outside thereof, and a plurality of pads to which bonding wires are electrically connected. A CPU core block, peripheral blocks, random logic blocks, and a gate array block are placed in the core macro portion. The respective blocks are electrically connected to one another by metal interconnections. The gate array block designed by a gate array system is layout-designed in accordance with a standard cell system or full custom system together with other blocks.

Abstract: To implement a method of laying out interconnections, which is capable of reducing a skew value of a predetermined signal and a delay in predetermined signal to the utmost, a region intended for a wiring layout employed in a CAD system is divided into a plurality of subregions and wiring regions dedicated to the predetermined signal in the respective subregions are set. The number of driver's stages in the respective subregions is set and the region is enlarged with the adjacent subregions identical in number of driver's stages as virtual subregions. Thus, the layout of wiring between the subregions is set.