Abstract: A scan test generation method includes dividing a single clock domain into a plurality of regions; incorporating a test pattern generation control circuit in each of the regions; selecting one of a skewed-load mode and a broadside mode as a test pattern generation mode by the test pattern generation control circuit for each region; generating a test pattern determined based on selected one of the test pattern generation mode for each region; and generating a test pattern such that the skewed-load mode and the broadside mode are mixed in a single clock domain.

Abstract: A scan test generation method includes dividing a single clock domain into a plurality of regions; incorporating a test pattern generation control circuit in each of the regions; selecting one of a skewed-load mode and a broadside mode as a test pattern generation mode by the test pattern generation control circuit for each region; generating a test pattern determined based on selected one of the test pattern generation mode for each region; and generating a test pattern such that the skewed-load mode and the broadside mode are mixed in a single clock domain.

Abstract: To improve a delay fault coverage without increasing an area overhead, provided is a scan test circuit including: scan flip-flops forming a clock domain that operates according to the same clock within a semiconductor integrated circuit including a target of a delay fault test; a test pattern generation mode control unit (scan flip-flop) that is supplied with the same clock as that supplied to the scan flip-flops, and selects one of a skewed-load mode and a broadside mode as a test pattern generation mode of the delay fault test; and a scan enable signal output unit (OR gate) that outputs a first scan enable signal, which is determined based on the test pattern generation mode, to the scan flip-flops.

Abstract: To improve a delay fault coverage without increasing an area overhead, provided is a scan test circuit including: scan flip-flops forming a clock domain that operates according to the same clock within a semiconductor integrated circuit including a target of a delay fault test; a test pattern generation mode control unit (scan flip-flop) that is supplied with the same clock as that supplied to the scan flip-flops, and selects one of a skewed-load mode and a broadside mode as a test pattern generation mode of the delay fault test; and a scan enable signal output unit (OR gate) that outputs a first scan enable signal, which is determined based on the test pattern generation mode, to the scan flip-flops.

Abstract: A method of generating a pattern for testing a logic circuit includes judging whether generation of a test pattern is to be undertaken. If it is judged that generation of a test pattern is to be undertaken, a fault is selected for which the test pattern is to be generated. Generation is attempted of at least one test pattern necessary for detecting the selected fault. Fault simulation is carried out to find a test pattern, from among copies of the at least one test pattern, by which the most undetected faults are detected. If at least one test pattern is generated, the test pattern is re-activated.

Abstract: A method of generating a pattern for testing a logic circuit, includes the steps of (a) judging whether generation of a test pattern is to be finished, (b) selecting a fault for which the test pattern is to be generated, if generation of the test pattern is judged to be continued in the step (a), (c) attempting generating at least one test pattern necessary for detecting the fault selected in the step (b), and (d) carrying out fault simulation to find a test pattern by which undetected faults are detected most, among copies of the at least one test pattern, and re-activating the thus found test pattern, if the at least one test pattern is generated in the step (c).

Abstract: A test pattern generating apparatus including circuit information/fault information input means 101, test pattern input generating means 102, test pattern input assigning means 103, logical simulation means 104, fault defining means 105, fault simulation means 106, fault extracting(detecting) means 107, initial test pattern extracting means 108, test pattern converting means 109 for assigning undefined values to an initial test pattern, final test pattern extracting means 110, test pattern generation judging means 111, all extracted test pattern merging means 112, and merged test pattern output means 413.