Patents by Inventor Hirohiko Ito
Hirohiko Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240045409Abstract: A line management assistance device (100) is connectable to at least two sensors installed on a line. The line management assistance device (100) includes a receiver (11) that receives a management condition specified as a condition for managing the line, and a display (12) that displays assistance information indicating a list of candidates for a sensor to be used to manage the line. The candidates are one or more sensors preassociated with a use condition of preregistered use conditions for the at least two sensors. The use condition has a degree of similarity to the management condition exceeding a threshold.Type: ApplicationFiled: June 15, 2021Publication date: February 8, 2024Applicant: Mitsubishi Electric CorporationInventors: Jun KIRITANI, Hirohiko ITO, Taro SHIBI, Takashi SAEKI, Hidematsu HAYASHI
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Publication number: 20230332902Abstract: A transfer guidance system includes at least one memory storing instructions, and at least one processor. The at least one processor is configured to execute the instructions to estimate operation time schedules of a plurality of transportation systems based on track records of operation of the plurality of the transportation systems and generates estimated data, accept request information including locations of departure and destination, generate guidance information for providing information about a route from the location of departure to the location of destination, the route extending over the plurality of the transportation systems, present the guidance information to a user.Type: ApplicationFiled: September 24, 2021Publication date: October 19, 2023Applicant: NEC CorporationInventors: Hirohiko ITO, Sachin Mishra, Akihiko Iketani
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Patent number: 10191829Abstract: According to one embodiment, a semiconductor device includes a memory-transfer control unit that controls data transfer between a memory and a sound unit. A plurality of sound data transfer routes are configured by one memory-transfer control unit and one sound unit. The semiconductor device outputs reproduction sound data via at least one sound data transfer route and acquires at least two pieces of recording sound data on account of one piece of reproduction sound data via at least two sound data transfer routes.Type: GrantFiled: July 18, 2015Date of Patent: January 29, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Hirohiko Ito
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Publication number: 20160055070Abstract: According to one embodiment, a semiconductor device includes a memory-transfer control unit that controls data transfer between a memory and a sound unit. A plurality of sound data transfer routes are configured by one memory-transfer control unit and one sound unit. The semiconductor device outputs reproduction sound data via at least one sound data transfer route and acquires at least two pieces of recording sound data on account of one piece of reproduction sound data via at least two sound data transfer routes.Type: ApplicationFiled: July 18, 2015Publication date: February 25, 2016Inventor: Hirohiko ITO
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Publication number: 20150311904Abstract: A semiconductor device includes a clock input circuit that receives an external clock signal, a PLL circuit for input timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to acquire input data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to a PLL circuit for input timing control as a delayed clock signal. The semiconductor device further includes a PLL circuit for output timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to output data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to the PLL circuit for output timing control as a delayed clock signal.Type: ApplicationFiled: June 10, 2015Publication date: October 29, 2015Inventors: Hajime Sasaki, Hirohiko Ito, Shikiko Nachi, Takanobu Naruse
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Patent number: 9083353Abstract: A semiconductor device includes a clock input circuit that receives an external clock signal, a PLL circuit for input timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to acquire input data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to a PLL circuit for input timing control as a delayed clock signal. The semiconductor device further includes a PLL circuit for output timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to output output data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to the PLL circuit for output timing control as a delayed clock signal.Type: GrantFiled: July 27, 2013Date of Patent: July 14, 2015Assignee: Renesas Electronics CorporationInventors: Hajime Sasaki, Hirohiko Ito, Shikiko Nachi, Takanobu Naruse
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Publication number: 20140289022Abstract: A basic behavior information acquirer (11) of a task assistance device (1) acquires basic behavior information that indicates behavior of a member. A task behavior information appender (12) appends, to the basic behavior information, task behavior information that indicates a pre-set classification of the behavior. A task flow calculator (13) calculates a task flow that interrelates the task behavior information based on attribute information of the basic behavior information to which the task behavior information is appended. An expected task flow acquirer (14) acquires an expected task flow that a member is supposed to perform. A task flow difference detector (15) detects difference between the task flow and the expected task flow. An outputter (71) outputs presentation information that indicates difference between the task flow and the expected task flow.Type: ApplicationFiled: September 28, 2012Publication date: September 25, 2014Applicant: NEC CORPORATIONInventors: Yuki Kamiya, Takao Shime, Hirohiko Ito, Kazuo Kunieda
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Publication number: 20140244358Abstract: In an aspect of the present invention, a need determination device includes a storage unit configured to store survey data in which an assessment value of a quantitatively or qualitatively assessable survey item is set at each textbook that is the same type as an object of which needs are to be determined, and need assessment data in which an assessment value of a need is set at each of the textbooks; a determination logic generation unit configured to generate a determination logic for determining a need based on the survey data and the need assessment data; and a determination unit configured to determine a need of the object by applying, to the determination logic, input data in which the assessment value of the survey item of the object of which needs are to be determined is set.Type: ApplicationFiled: February 24, 2014Publication date: August 28, 2014Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Mayumi Saito, Takashi Sonoda, Rong Wang, Hirohiko Ito, Koji Imakita
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Publication number: 20140043075Abstract: A semiconductor device includes a clock input circuit that receives an external clock signal, a PLL circuit for input timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to acquire input data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to a PLL circuit for input timing control as a delayed clock signal. The semiconductor device further includes a PLL circuit for output timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to output output data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to the PLL circuit for output timing control as a delayed clock signal.Type: ApplicationFiled: July 27, 2013Publication date: February 13, 2014Applicant: Renesas Mobile CorporationInventors: Hajime Sasaki, Hirohiko Ito, Shikiko Nachi, Takanobu Naruse
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Patent number: 7664321Abstract: This invention provides the following environment. That is, an original document file corresponding to a document to be copied is specified from image data of that document to be copied, and a print process is made based on the specified file so as to prevent deterioration of image quality. Also, when a document to be copied is not registered, a registration process is executed to suppress deterioration of image quality in an early stage. Furthermore, since the document is converted into vector data, re-use of such document is facilitated, and deterioration of image quality can be suppressed even when an image process such as enlargement or the like is made. To this end, when an original digital file cannot be specified, an apparatus of this embodiment executes a vectorization process (S54), converts the obtained vector data into a data format that can be re-used by an application (S55), and registers the converted file in a file server (S56).Type: GrantFiled: January 27, 2004Date of Patent: February 16, 2010Assignee: Canon Kabushiki KaishaInventors: Shigeo Fukuoka, Hiroshi Tanioka, Akihiro Usami, Ken-Ichi Ohta, Kitahiro Kaneda, Hirohiko Ito, Shinichi Kato, Tomohiro Akiba, Tomotoshi Kanatsu, Reiji Misawa, Yoshihide Terao, Mitsuru Uzawa
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Patent number: 7391917Abstract: Stored digital data is searched for on the basis of an input image, difference information is extracted by comparing the retrieved digital data and the input image, and the difference information is composited to the digital data. Digital data generated by composition is stored. When no digital data is retrieved, the input image is converted into vector data, and the image that has been converted into the vector data is stored as digital data. Obtained region segmentation information and an input image are composited, the composite image is displayed on an operation screen of an MFP, and a rectangular block to be vectorized is designated as a specific region from the displayed region segmentation information. A user designates the specific region by designating rectangular blocks in an image using a pointing device.Type: GrantFiled: February 11, 2004Date of Patent: June 24, 2008Assignee: Canon Kabushiki KaishaInventors: Ken-ichi Ohta, Hiroshi Tanioka, Akihiro Usami, Kitahiro Kaneda, Hirohiko Ito, Shinichi Kato, Tomohiro Akiba, Tomotoshi Kanatsu, Reiji Misawa, Yoshihide Terao, Mitsuru Uzawa
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Patent number: 7349577Abstract: This invention provides an image processing method which allows easy re-use of image information that is stored to minimize deterioration of image quality and the storage capacity. Storage means is searched for original digital data corresponding to each input image. If no original digital data is found, the input image is converted into vector data, and is stored as digital data in the storage means. A sheet including at least one of information associated with the found original digital data when the original digital data is found in the search step and information associated with digital data which is obtained by converting the image into the vector data in the vectorization step and is stored in the storage step when no original digital data is found in the search step is generated, thus providing a sheet that allows easy re-use.Type: GrantFiled: February 20, 2004Date of Patent: March 25, 2008Assignee: Canon Kabushiki KaishaInventors: Kitahiro Kaneda, Hiroshi Tanioka, Akihiro Usami, Ken-ichi Ohta, Hirohiko Ito, Shinichi Kato, Tomohiro Akiba, Tomotoshi Kanatsu, Reiji Misawa, Yoshihide Terao, Mitsuru Uzawa
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Patent number: 7206869Abstract: Image data scanned by way of a scanner controller is transferred from a memory controller to a memory by way of a G bus. A CPU reduces the image data stored in the memory by thinning processing or the like, and displays the image data on an operation panel by way of a B bus and interface. In this manner, an image can be input using the first bus while data transferred by way of the first bus is output by way of the second bus. This enables processing using image data which is being input, such as processing of immediately displaying an input image.Type: GrantFiled: August 25, 2004Date of Patent: April 17, 2007Assignee: Canon Kabushiki KaishaInventors: Junichi Shishizuka, Atsushi Date, Yoichi Takaragi, Hirohiko Ito, Hideyuki Makitani
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Patent number: 7023571Abstract: A method to enhance the copy or printout efficiency and decrease the number of output jobs that are abandoned because of undesirable outputs. Abort of output due to absence of sheets or staples, overload of a delivery tray, or the like is predicted. If output abort is determined, data is removed from an output queue and re-registered as an output reserve job at the end of the queue.Type: GrantFiled: July 28, 2004Date of Patent: April 4, 2006Assignee: Canon Kabushiki KaishaInventors: Bungo Shimada, Hiroshi Sumio, Hirohiko Ito, Nobuaki Miyahara
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Publication number: 20060045386Abstract: This invention provides the following environment. That is, an original document file corresponding to a document to be copied is specified from image data of that document to be copied, and a print process is made based on the specified file so as to prevent deterioration of image quality. Also, when a document to be copied is not registered, a registration process is executed to suppress deterioration of image quality in an early stage. Furthermore, since the document is converted into vector data, re-use of such document is facilitated, and deterioration of image quality can be suppressed even when an image process such as enlargement or the like is made. To this end, when an original digital file cannot be specified, an apparatus of this embodiment executes a vectorization process (S54), converts the obtained vector data into a data format that can be re-used by an application (S55), and registers the converted file in a file server (S56).Type: ApplicationFiled: January 27, 2004Publication date: March 2, 2006Inventors: Shigeo Fukuoka, Hiroshi Tanioka, Akihiro Usami, Ken-ichi Ohta, Kitahiro Kaneda, Hirohiko Ito, Shinichi Kato, Tomohiro Akiba, Tomotoshi Kanatsu, Reiji Misawa, Yoshihide Terao, Mitsuru Uzawa
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Patent number: 6989908Abstract: Image is processing of one image processing unit to be performed is decided into an image input job in which image data is input from an image input section and an image output job in which image data is output to an image output section. Execution of the image input job and that of the image output job are controlled independently. After a preceding image input job is finished, a new image input job is started before the image output job corresponding to the preceding image input job is finished.Type: GrantFiled: October 14, 1998Date of Patent: January 24, 2006Assignee: Canon Kabushiki KaishaInventor: Hirohiko Ito
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Patent number: 6980320Abstract: In an image forming apparatus incorporating an image forming unit capable of execution in a layout print mode in which a plurality of pages of image data is formed on a single sheet, whether or not to permit the image forming unit to execute in the layout print mode for a plurality of sets of image data to be laid out in the layout print mode is controlled based on the image property information of the plurality of image data, so that layout functions desired by users are provided and ease of operation by the users is improved without incurring excessive processes or additional cost.Type: GrantFiled: May 30, 2002Date of Patent: December 27, 2005Assignee: Canon Kabushiki KaishaInventor: Hirohiko Ito
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Patent number: 6980310Abstract: A method to enhance the copy or printout efficiency and decrease the number of output jobs that are abandoned because of undesirable outputs. Abort of output due to absence of sheets or staples, overload of a delivery tray, or the like is predicted. If output abort is determined, data is removed from an output queue and re-registered as an output reserve job at the end of the queue.Type: GrantFiled: June 28, 1999Date of Patent: December 27, 2005Assignee: Canon Kabushiki KaishaInventors: Bungo Shimada, Hiroshi Sumio, Hirohiko Ito, Nobuaki Miyahara
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Patent number: 6850995Abstract: Image data scanned by way of a scanner controller is transferred from a memory controller to a memory by way of a G bus. A CPU reduces the image data stored in the memory by thinning processing or the like, and displays the image data on an operation panel by way of a B bus and interface. In this manner, an image can be input using the first bus while data transferred by way of the first bus is output by way of the second bus. This enables processing using image data which is being input, such as processing of immediately displaying an input image.Type: GrantFiled: January 27, 2000Date of Patent: February 1, 2005Assignee: Canon Kabushiki KaishaInventors: Junichi Shishizuka, Atsushi Date, Yoichi Takaragi, Hirohiko Ito, Hideyuki Makitani
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Publication number: 20050021883Abstract: Image data scanned by way of a scanner controller is transferred from a memory controller to a memory by way of a G bus. A CPU reduces the image data stored in the memory by thinning processing or the like, and displays the image data on an operation panel by way of a B bus and interface. In this manner, an image can be input using the first bus while data transferred by way of the first bus is output by way of the second bus. This enables processing using image data which is being input, such as processing of immediately displaying an input image.Type: ApplicationFiled: August 25, 2004Publication date: January 27, 2005Applicant: CANON KABUSHIKI KAISHAInventors: Junichi Shishizuka, Atsushi Date, Yoichi Takaragi, Hirohiko Ito, Hideyuki Makitani