Abstract: A semiconductor device has a dummy pattern including an underlying layer which is formed on a semiconductor substrate and in which a plurality of word lines from N−2 to N+2 are arranged in parallel, a plurality of blocks each of which has a plurality of dummy sheets arranged in such a way that each of them spreads over the two word lines neighboring in the direction along the word lines from N−2 to N+2, and a plurality of dummy sheets arranged between the plurality of blocks in such a way that each of them spreads over the two word lines neighboring between the blocks.

Abstract: A semiconductor device has a dummy pattern including an underlying layer which is formed on a semiconductor substrate and in which a plurality of word lines from N−2 to N+2 are arranged in parallel, a plurality of blocks each of which has a plurality of dummy sheets arranged in such a way that each of them spreads over the two word lines neighboring in the direction along the word lines from N−2 to N+2, and a plurality of dummy sheets arranged between the plurality of blocks in such a way that each of them spreads over the two word lines neighboring between the blocks.

Abstract: NMOS transistors which are provided adjacently to each other in the direction of the formation of bit lines between word lines are paired. The drains of the NMOS transistors are connected in common through a common node to form a memory cell. Between the common node and the bit line is provided a region where a contact is placed. Furthermore, regions where the contact is placed in the respective NMOS transistors are provided on a layout. By these combinations, data are stored.