Patents by Inventor Hirohiko Yamamoto
Hirohiko Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9337147Abstract: A semiconductor device includes grooves defining an active region, including a MISFET, and dummy regions. A first interlayer insulation film is formed over the MISFET, the active region and the dummy regions. A first wiring, and first and second dummy wirings are formed over the first interlayer insulation film. A second interlayer insulation film is formed over the first wiring and the dummy wirings. The second dummy wirings are arranged between the first wiring and the first dummy wirings, and the pitch of the first dummy wirings is larger than that of the second dummy wirings. In planar view, the first and second dummy wirings are arranged over the dummy regions, and the size of each of the first dummy wirings is larger than size of each of the second dummy wirings. The first wiring and the first and second dummy wirings are formed of copper as a major component.Type: GrantFiled: June 19, 2015Date of Patent: May 10, 2016Assignee: Renesas Electronics CorporationInventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
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Publication number: 20150287679Abstract: A semiconductor device includes grooves defining an active region, including a MISFET, and dummy regions. A first interlayer insulation film is formed over the MISFET, the active region and the dummy regions. A first wiring, and first and second dummy wirings are formed over the first interlayer insulation film. A second interlayer insulation film is formed over the first wiring and the dummy wirings. The second dummy wirings are arranged between the first wiring and the first dummy wirings, and the pitch of the first dummy wirings is larger than that of the second dummy wirings. In planar view, the first and second dummy wirings are arranged over the dummy regions, and the size of each of the first dummy wirings is larger than size of each of the second dummy wirings. The first wiring and the first and second dummy wirings are formed of copper as a major component.Type: ApplicationFiled: June 19, 2015Publication date: October 8, 2015Inventors: Kenichi KURODA, Kozo WATANABE, Hirohiko YAMAMOTO
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Patent number: 9064926Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.Type: GrantFiled: December 9, 2013Date of Patent: June 23, 2015Assignee: Renesas Electronics CorporationInventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
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Publication number: 20140099770Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.Type: ApplicationFiled: December 9, 2013Publication date: April 10, 2014Applicants: Hitachi ULSI Systems Co., Ltd., Renesas Electronics CorporationInventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
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Patent number: 8604505Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.Type: GrantFiled: April 8, 2013Date of Patent: December 10, 2013Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
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Publication number: 20130241029Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.Type: ApplicationFiled: April 8, 2013Publication date: September 19, 2013Applicants: HITACHI ULSI SYSTEMS CO., LTD., RENESAS ELECTRONICS CORPORATIONInventors: Kenichi KURODA, Kozo WATANABE, Hirohiko YAMAMOTO
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Patent number: 8426969Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.Type: GrantFiled: January 31, 2012Date of Patent: April 23, 2013Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
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Patent number: 8334481Abstract: A mounting table body made of ceramic includes power-receiving conductor portions and buried therein. A surface of mounting table body is formed with a recessed connection hole and a connection terminal electrically jointed to the power-receiving conductor portion and exposed into the connection hole, the connection terminal being made of a high-melting-point metal, an alloy thereof or a compound thereof. A power-feeding line member provided with a power-feeding connector portion is inserted at its leading end portion into the connection hole to feed electricity to the power-receiving conductor portion. A stress relaxing member is interposed between the connection terminal and the power-feeding connector portion. The stress relaxing member and the connection terminal are jointed together by a brazing material. The stress relaxing member is made of a metal free from cobalt and nickel or an alloy thereof.Type: GrantFiled: July 17, 2009Date of Patent: December 18, 2012Assignee: Tokyo Electron LimitedInventors: Tomohito Komatsu, Hirohiko Yamamoto, Daisuke Toriya
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Publication number: 20120126360Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.Type: ApplicationFiled: January 31, 2012Publication date: May 24, 2012Inventors: Kenichi KURODA, Kozo Watanabe, Hirohiko Yamamoto
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Patent number: 8119495Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.Type: GrantFiled: April 28, 2011Date of Patent: February 21, 2012Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
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Publication number: 20110207288Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.Type: ApplicationFiled: April 28, 2011Publication date: August 25, 2011Inventors: Kenichi KURODA, Kozo Watanabe, Hirohiko Yamamoto
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Patent number: 7948086Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.Type: GrantFiled: March 1, 2010Date of Patent: May 24, 2011Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
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Publication number: 20100323313Abstract: There is provided a stage structure which can prevent the formation of a cool spot in the central portion of a stage, thereby preventing breakage of the stage, and can enhance the in-plane uniformity of heat treatment of a processing object. The stage structure, provided in a treatment container of a heat treatment apparatus, for placing thereon a semiconductor wafer W as a processing object to be heat treated, includes: a stage 52 for placing the processing object on it; and a cylindrical support post 54 jointed to the center of the lower surface of the stage and supporting the stage. A heat reflecting section 56 is provided at an upper position within the support post and close to the lower surface of the stage. The use of the heat reflecting section 56 prevents the formation of a cool spot in the central portion of the stage 54.Type: ApplicationFiled: March 13, 2009Publication date: December 23, 2010Applicant: TOKYO ELECRON LIMITEDInventors: Daisuke Toriya, Hirohiko Yamamoto
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Publication number: 20100155857Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.Type: ApplicationFiled: March 1, 2010Publication date: June 24, 2010Inventors: Kenichi KURODA, Kozo Watanabe, Hirohiko Yamamoto
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Patent number: 7687914Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.Type: GrantFiled: October 30, 2007Date of Patent: March 30, 2010Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
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Publication number: 20090277895Abstract: A mounting table body made of ceramic includes power-receiving conductor portions and buried therein. A surface of mounting table body is formed with a recessed connection hole and a connection terminal electrically jointed to the power-receiving conductor portion and exposed into the connection hole, the connection terminal being made of a high-melting-point metal, an alloy thereof or a compound thereof. A power-feeding line member provided with a power-feeding connector portion is inserted at its leading end portion into the connection hole to feed electricity to the power-receiving conductor portion. A stress relaxing member is interposed between the connection terminal and the power-feeding connector portion. The stress relaxing member and the connection terminal are jointed together by a brazing material. The stress relaxing member is made of a metal free from cobalt and nickel or an alloy thereof.Type: ApplicationFiled: July 17, 2009Publication date: November 12, 2009Applicant: TOKYO ELECTRON LIMITEDInventors: Tomohito KOMATSU, Hirohiko Yamamoto, Daisuke Toriya
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Patent number: 7589423Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.Type: GrantFiled: May 24, 2007Date of Patent: September 15, 2009Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
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Patent number: 7411302Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.Type: GrantFiled: May 10, 2006Date of Patent: August 12, 2008Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
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Patent number: 7402473Abstract: A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.Type: GrantFiled: April 19, 2005Date of Patent: July 22, 2008Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Norio Suzuki, Yasushi Matsuda, Yasuko Yoshida, Hirohiko Yamamoto, Masamichi Kobayashi, Akira Takamatsu, Hirofumi Shimizu, Kazushi Fukuda, Shinichi Horibe, Toshio Nozoe
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Publication number: 20070222080Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.Type: ApplicationFiled: May 24, 2007Publication date: September 27, 2007Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto