Patents by Inventor Hirohisa Nakayama

Hirohisa Nakayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing semiconductor device and method of treating electrical connection section
    Patent number: 7608479
    Abstract: A method of manufacturing a semiconductor device includes: applying a paste containing acid to an electrical connection section which is electrically connected with a semiconductor substrate; removing the paste from the electrical connection section by washing the electrical connection section; and providing a conductive material to the electrical connection section.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: October 27, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Hirohisa Nakayama, Shiro Sato, Masanobu Shoji, Hitoshi Nosaka
  • Semiconductor device, electronic device, electronic equipment, method of manufacturing semiconductor device, and method of manufacturing electronic device
    Patent number: 7230329
    Abstract: A method is provided to realize a three-dimensional mounting structure of different types of packages. By bonding protruding electrodes onto lands, which are formed on a first carrier substrate, second and third carrier substrates are mounted on the first carrier substrate such that ends of the second and third carrier substrates are arranged above a semiconductor chip.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: June 12, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Toshihiro Sawamoto, Hirohisa Nakayama, Akiyoshi Aoyagi
  • Method of manufacturing semiconductor device and method of treating electrical connection section
    Publication number: 20060160347
    Abstract: A method of manufacturing a semiconductor device includes: applying a paste containing acid to an electrical connection section which is electrically connected with a semiconductor substrate; removing the paste from the electrical connection section by washing the electrical connection section; and providing a conductive material to the electrical connection section.
    Type: Application
    Filed: January 17, 2006
    Publication date: July 20, 2006
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hirohisa Nakayama, Shiro Sato, Masanobu Shoji, Hitoshi Nosaka
  • Semiconductor device, electronic device, electronic equipment, method of manufacturing semiconductor device, and method of manufacturing electronic device
    Publication number: 20040222534
    Abstract: A method is provided to realize a three-dimensional mounting structure of different types of packages. By bonding protruding electrodes onto lands, which are formed on a first carrier substrate, second and third carrier substrates are mounted on the first carrier substrate such that ends of the second and third carrier substrates are arranged above a semiconductor chip.
    Type: Application
    Filed: February 6, 2004
    Publication date: November 11, 2004
    Inventors: Toshihiro Sawamoto, Hirohisa Nakayama, Akiyoshi Aoyagi
  • Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
    Publication number: 20040075163
    Abstract: A semiconductor device having a semiconductor chip, a sheet on which is mounted the semiconductor chip, a sealing section in which the semiconductor chip and the sheet are sealed, and a plurality of leads electrically connected to the semiconductor chip by wires in the sealing section. The leads include a first lead to which the sheet is bonded and a second lead to which the sheet is not bonded.
    Type: Application
    Filed: July 10, 2003
    Publication date: April 22, 2004
    Applicant: Seiko Epson Corporation
    Inventor: Hirohisa Nakayama
  • Semiconductor device and method of fabricating the same, circuit board, and electronic equipment
    Patent number: 6621172
    Abstract: A first semiconductor chip is mounted on a substrate on which an interconnect pattern is formed, and a surface of the first semiconductor chip having electrodes faces the substrate. A second semiconductor chip is mounted on the first semiconductor chip. Electrodes of the second semiconductor chip are electrically connected to the interconnect pattern by wires. A first resin is provided between the first semiconductor chip and the substrate, and a second resin which differs from the first resin seals the first and second semiconductor chips.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: September 16, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Hirohisa Nakayama, Jun Taniguchi, Takashi Abe, Toshinori Nakayama
  • Semiconductor device and method of fabricating the same, circuit board, and electronic equipment
    Publication number: 20020004258
    Abstract: A first semiconductor chip is mounted on a substrate on which an interconnect pattern is formed, and a surface of the first semiconductor chip having electrodes faces the substrate. A second semiconductor chip is mounted on the first semiconductor chip. Electrodes of the second semiconductor chip are electrically connected to the interconnect pattern by wires. A first resin is provided between the first semiconductor chip and the substrate, and a second resin which differs from the first resin seals the first and second semiconductor chips.
    Type: Application
    Filed: April 27, 2001
    Publication date: January 10, 2002
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hirohisa Nakayama, Jun Taniguchi, Takashi Abe, Toshinori Nakayama