Patents by Inventor Hirohisa OTSUKI

Hirohisa OTSUKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230059212
    Abstract: A solid-state imaging device includes an N-type semiconductor layer, an element layer including a photoelectric conversion element and an active element, an interconnect layer providing an interconnect for the active element, and an element isolation trench penetrating the semiconductor layer. The element layer includes a P-type region and an N-type region. A first hole storage layer is formed on a surface of the semiconductor layer on a side opposite to the element layer. A second hole storage layer is formed in contact portions of the semiconductor layer and the element layer with the element isolation trench. The P-type region of the element layer and the first hole storage layer are connected to each other by the second hole storage layer.
    Type: Application
    Filed: February 19, 2021
    Publication date: February 23, 2023
    Applicants: TOWER PARTNERS SEMICONDUCTOR CO., LTD., TOWER SEMICONDUCTOR LTD.
    Inventors: Masahiro ODA, Hiroki TAKAHASHI, Hiroyuki DOI, Hirohisa OTSUKI
  • Patent number: 11011557
    Abstract: A plurality of pixels are two-dimensionally arranged on a semiconductor substrate. Each of the pixels includes: two photodiodes each generating charge by photoelectric conversion; first and second memories spaced apart from each other between the two photodiodes as viewed in cross section; a first readout gate reading charge from the two photodiodes to the first memory; and a second readout gate reading charge from the two photodiodes to the second memory.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: May 18, 2021
    Assignee: Tower Partners Semiconductor Co., Ltd.
    Inventors: Masahiro Oda, Hirohisa Otsuki
  • Publication number: 20180226439
    Abstract: A plurality of pixels are two-dimensionally arranged on a semiconductor substrate. Each of the pixels includes: two photodiodes each generating charge by photoelectric conversion; first and second memories spaced apart from each other between the two photodiodes as viewed in cross section; a first readout gate reading charge from the two photodiodes to the first memory; and a second readout gate reading charge from the two photodiodes to the second memory.
    Type: Application
    Filed: March 29, 2018
    Publication date: August 9, 2018
    Inventors: Masahiro ODA, Hirohisa OTSUKI
  • Publication number: 20180219035
    Abstract: A plurality of pixels which are two-dimensionally arranged on a semiconductor substrate includes: a photodiode generating charge by photoelectric conversion; two readout gates each reading charge from the photodiode; and two memories each receiving the charge from the photodiode through an associated one of the two readout gates and temporarily retaining the charge received. Two of the pixels adjacent to each other in a row direction share one of the two readout gates.
    Type: Application
    Filed: March 29, 2018
    Publication date: August 2, 2018
    Inventor: Hirohisa OTSUKI