Abstract: Provided is a guide rail cleaning device, including: a first cleaning portion including a first cleaning member configured to clean a driving-roller guide rail for a step; a second cleaning portion including a second cleaning member configured to clean a trailing-roller guide rail; and a mounting plate. The mounting plate is removably mounted to a step shaft having a driving roller fixed thereto. The first cleaning portion and the second cleaning portion are mounted to the mounting plate. The first cleaning member is brought into abutment against the driving-roller guide rail. The second cleaning member is brought into abutment against the trailing-roller guide rail. With this, the driving-roller guide rail and the trailing-roller guide rail are simultaneously cleaned through use of the first cleaning member and the second cleaning member.

Abstract: Provided is a guide rail cleaning device, including: a first cleaning portion including a first cleaning member configured to clean a driving-roller guide rail for a step; a second cleaning portion including a second cleaning member configured to clean a trailing-roller guide rail; and a mounting plate. The mounting plate is removably mounted to a step shaft having a driving roller fixed thereto. The first cleaning portion and the second cleaning portion are mounted to the mounting plate. The first cleaning member is brought into abutment against the driving-roller guide rail. The second cleaning member is brought into abutment against the trailing-roller guide rail. With this, the driving-roller guide rail and the trailing-roller guide rail are simultaneously cleaned through use of the first cleaning member and the second cleaning member.

Abstract: A semiconductor substrate has on its major surface a N.sup.- drain region, within which a P base region is selectively formed. In the P base region is formed a P.sup.+ base region which has a higher impurity concentration than that of the P base region. A source region is selectively formed across and within the P base region and P.sup.+ base region. The source region has a lightly doped N source region and a heavily doped N.sup.+ source region. The N.sup.+ source region is entirely formed within the P.sup.+ base region so as not to form an N.sup.+ P junction which is high in emitter injection efficiency and thereby to make a parasitic transistor hard to operate. Furthermore, the N source region is formed smaller in depth than the P.sup.+ source region so as to decrease the base spreading resistance of the parasitic transistor and thereby to make the parasitic transistor hard to operate. A gate electrode is formed over a channel region, which is a portion of the P base region that is sandwiched between the N.

Abstract: In a power MOS FET and the method of manufacturing such FET, in which a material, such as platinum, having a small resistivity compensation effect is diffused as a lifetime killer into the vicinity of a PN diode junction formed by the drain region and the base region. The diffusion is made through an opening formed in a covering insulator layer. An example of the lifetime killer is platinum and the preferable temperature range for diffusing platinum is not higher than 900.degree. C.

Abstract: In a power MOS FET and the method of manufacturing such FET, in which a material, such as platinum, having a small resistivity compensation effect is diffused as a lifetime killer into the vicinity of a PN diode junction formed by the drain region and the base region. The diffusion is made through an opening formed in a covering insulator layer. An example of the lifetime killer is platinum and the preferable temperature range for diffusing platinum is not higher than 900.degree.C.