Patents by Inventor Hiroi Oka
Hiroi Oka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240063059Abstract: In a case where a crack occurs in a dicing step, the crack can be suppressed from proceeding toward an element region. A first scribe region and a second scribe region that both define an element region are formed in a main surface of a semiconductor wafer. In the first scribe region, an evaluation-deep-trench group including an evaluation-deep-trench-first portion and an evaluation-deep-trench-second portion is formed. The evaluation-deep-trench-first portion is formed in a first region. The evaluation-deep-trench-second portion has a width in an X-axis direction, and is formed in a bar shape extending in a Y-axis direction, in a second region located between the first region and the element region.Type: ApplicationFiled: May 3, 2023Publication date: February 22, 2024Inventors: Koichi ANDO, Toshiyuki HATA, Kosuke KITAICHI, Hiroi OKA
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Patent number: 10395967Abstract: Provided is a method of manufacturing a semiconductor device with improved manufacturing efficiency for the semiconductor device. The method of manufacturing a semiconductor device includes the steps of: (a) forming a circuit at a front surface side of a wafer (semiconductor wafer) having the front surface and a back surface opposite to the front surface; (b) grinding the back surface of the wafer that has a center part (first part) and a peripheral edge part (second part) surrounding a periphery of the center part in such a manner that the center part is thinner than the peripheral edge part; (c) attaching an upper surface (bonding surface) of a holding tape to the front surface of the wafer; and (d) separating the center part from the peripheral edge part by cutting a part of the center part with a blade (rotary blade) while the wafer is held by the first tape.Type: GrantFiled: June 20, 2017Date of Patent: August 27, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takamitsu Yoshihara, Takahiro Kainuma, Hiroi Oka
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Patent number: 10388597Abstract: A die bonding process for assembling a semiconductor device includes the steps of applying a sintered-silver-use paste to each of a plurality of first regions on an upper surface of a chip mounting part, drying the sintered-silver-use paste and applying a silver paste to a second region located between/among the respective first regions. Further, the process includes the step of mounting a semiconductor chip onto the chip mounting part in such a manner that a rear surface of the semiconductor chip faces an upper surface of the chip mounting part with the sintered-silver-use paste and the silver paste being interposed. After mounting the chip, part of each of first, second, third and fourth corners of a principal surface of the semiconductor chip is located in each of the first regions.Type: GrantFiled: May 22, 2018Date of Patent: August 20, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masatoshi Sugiura, Hiroi Oka
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Patent number: 10347567Abstract: In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.Type: GrantFiled: June 27, 2018Date of Patent: July 9, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Atsushi Nishikizawa, Yuichi Yato, Hiroi Oka, Tadatoshi Danno, Hiroyuki Nakamura
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Patent number: 10262927Abstract: Reliability of a semiconductor device is improved. For this, embodied is a basic idea that a semiconductor chip (CHP1) mounted on an Ag layer (AGL) is fixed by using a temporarily fixing material (TA) having tackiness without forming the temporarily fixing material (TA) on a surface of the Ag layer (AGL) having a porous structure as much as possible, is realized. More specifically, the temporarily fixing material (TA) is supplied so as to have a portion made in contact with a chip mounting part (TAB), and the semiconductor chip (CHP1) is also mounted on the Ag layer (AGL) so that one portion of a rear surface of the semiconductor chip (CHP1) is made in contact with the temporarily fixing material (TA).Type: GrantFiled: July 23, 2015Date of Patent: April 16, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazunori Hasegawa, Hiroi Oka
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Publication number: 20190006268Abstract: A die bonding process for assembling a semiconductor device includes the steps of applying a sintered-silver-use paste to each of a plurality of first regions on an upper surface of a chip mounting part, drying the sintered-silver-use paste and applying a silver paste to a second region located between/among the respective first regions. Further, the process includes the step of mounting a semiconductor chip onto the chip mounting part in such a manner that a rear surface of the semiconductor chip faces an upper surface of the chip mounting part with the sintered-silver-use paste and the silver paste being interposed. After mounting the chip, part of each of first, second, third and fourth corners of a principal surface of the semiconductor chip is located in each of the first regions.Type: ApplicationFiled: May 22, 2018Publication date: January 3, 2019Inventors: Masatoshi SUGIURA, Hiroi OKA
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Publication number: 20180315685Abstract: In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.Type: ApplicationFiled: June 27, 2018Publication date: November 1, 2018Inventors: Atsushi NISHIKIZAWA, Yuichi YATO, Hiroi OKA, Tadatoshi DANNO, Hiroyuki NAKAMURA
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Publication number: 20180247884Abstract: Reliability of a semiconductor device is improved. For this, embodied is a basic idea that a semiconductor chip (CHP1) mounted on an Ag layer (AGL) is fixed by using a temporarily fixing material (TA) having tackiness without forming the temporarily fixing material (TA) on a surface of the Ag layer (AGL) having a porous structure as much as possible, is realized. More specifically, the temporarily fixing material (TA) is supplied so as to have a portion made in contact with a chip mounting part (TAB), and the semiconductor chip (CHP1) is also mounted on the Ag layer (AGL) so that one portion of a rear surface of the semiconductor chip (CHP1) is made in contact with the temporarily fixing material (TA).Type: ApplicationFiled: July 23, 2015Publication date: August 30, 2018Inventors: Kazunori HASEGAWA, Hiroi OKA
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Patent number: 10037932Abstract: In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.Type: GrantFiled: March 30, 2015Date of Patent: July 31, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Atsushi Nishikizawa, Yuichi Yato, Hiroi Oka, Tadatoshi Danno, Hiroyuki Nakamura
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Patent number: 9922905Abstract: A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin. Also, a length of the first part of the chip mounting part in the first direction is larger than a length of the semiconductor chip in the first direction, in a plan view.Type: GrantFiled: February 28, 2017Date of Patent: March 20, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yuichi Yato, Hiroi Oka, Noriko Okunishi, Keita Takada
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Publication number: 20170287765Abstract: Provided is a method of manufacturing a semiconductor device with improved manufacturing efficiency for the semiconductor device. The method of manufacturing a semiconductor device includes the steps of: (a) forming a circuit at a front surface side of a wafer (semiconductor wafer) having the front surface and a back surface opposite to the front surface; (b) grinding the back surface of the wafer that has a center part (first part) and a peripheral edge part (second part) surrounding a periphery of the center part in such a manner that the center part is thinner than the peripheral edge part; (c) attaching an upper surface (bonding surface) of a holding tape to the front surface of the wafer; and (d) separating the center part from the peripheral edge part by cutting a part of the center part with a blade (rotary blade) while the wafer is held by the first tape.Type: ApplicationFiled: June 20, 2017Publication date: October 5, 2017Inventors: Takamitsu YOSHIHARA, Takahiro KAINUMA, Hiroi OKA
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Publication number: 20170221800Abstract: In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.Type: ApplicationFiled: March 30, 2015Publication date: August 3, 2017Inventors: Atsushi NISHIKIZAWA, Yuichi YATO, Hiroi OKA, Tadatoshi DANNO, Hiroyuki NAKAMURA
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Patent number: 9716027Abstract: Provided is a method of manufacturing a semiconductor device with improved manufacturing efficiency for the semiconductor device. The method of manufacturing a semiconductor device includes the steps of: (a) forming a circuit at a front surface side of a wafer (semiconductor wafer) having the front surface and a back surface opposite to the front surface; (b) grinding the back surface of the wafer that has a center part (first part) and a peripheral edge part (second part) surrounding a periphery of the center part in such a manner that the center part is thinner than the peripheral edge part; (c) attaching an upper surface (bonding surface) of a holding tape to the front surface of the wafer; and (d) separating the center part from the peripheral edge part by cutting a part of the center part with a blade (rotary blade) while the wafer is held by the first tape.Type: GrantFiled: January 27, 2016Date of Patent: July 25, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takamitsu Yoshihara, Takahiro Kainuma, Hiroi Oka
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Publication number: 20170170100Abstract: A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin. Also, a length of the first part of the chip mounting part in the first direction is larger than a length of the semiconductor chip in the first direction, in a plan view.Type: ApplicationFiled: February 28, 2017Publication date: June 15, 2017Inventors: Yuichi YATO, Hiroi OKA, Noriko OKUNISHI, Keita TAKADA
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Patent number: 9607940Abstract: A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin. Also, a length of the first part of the chip mounting part in the first direction is larger than a length of the semiconductor chip in the first direction, in a plan view.Type: GrantFiled: July 5, 2013Date of Patent: March 28, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yuichi Yato, Hiroi Oka, Noriko Okunishi, Keita Takada
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Publication number: 20160293473Abstract: Provided is a method of manufacturing a semiconductor device with improved manufacturing efficiency for the semiconductor device. The method of manufacturing a semiconductor device includes the steps of: (a) forming a circuit at a front surface side of a wafer (semiconductor wafer) having the front surface and a back surface opposite to the front surface; (b) grinding the back surface of the wafer that has a center part (first part) and a peripheral edge part (second part) surrounding a periphery of the center part in such a manner that the center part is thinner than the peripheral edge part; (c) attaching an upper surface (bonding surface) of a holding tape to the front surface of the wafer; and (d) separating the center part from the peripheral edge part by cutting a part of the center part with a blade (rotary blade) while the wafer is held by the first tape.Type: ApplicationFiled: January 27, 2016Publication date: October 6, 2016Inventors: Takamitsu YOSHIHARA, Takahiro KAINUMA, Hiroi OKA
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Publication number: 20160204057Abstract: A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin. Also, a length of the first part of the chip mounting part in the first direction is larger than a length of the semiconductor chip in the first direction, in a plan view.Type: ApplicationFiled: July 5, 2013Publication date: July 14, 2016Inventors: Yuichi YATO, Hiroi OKA, Noriko OKUNISHI, Keita TAKADA
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Publication number: 20140264383Abstract: A semiconductor device includes a die pad, an SiC chip mounted on the die pad, a porous first sintered Ag layer bonding the die pad and the SiC chip, and a reinforcing resin portion covering a surface of the first sintered Ag layer and formed in a fillet shape. The semiconductor device further includes a source lead electrically connected to a source electrode of the SiC chip, a gate lead electrically connected to a gate electrode, a drain lead electrically connected to a drain electrode, and a sealing body which covers the SiC chip, the first sintered Ag layer, and a part of the die pad, and the reinforcing resin portion covers a part of a side surface of the SiC chip.Type: ApplicationFiled: March 14, 2014Publication date: September 18, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Ryoichi KAJIWARA, Takuya NAKAJO, Katsuo ARAI, Yuichi YATO, Hiroi OKA, Hiroshi HOZOJI
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Patent number: 8643185Abstract: A die bonding portion is metallically bonded by well-conductive Cu metal powders with a maximum particle diameter of about 15 ?m to 200 ?m and adhesive layers of Ag, and minute holes are evenly dispersed in a joint layer. With this structure, the reflow resistance of about 260° C. and reliability under thermal cycle test can be ensured without using lead.Type: GrantFiled: October 7, 2008Date of Patent: February 4, 2014Assignee: Renesas Electronics CorporationInventors: Ryoichi Kajiwara, Kazutoshi Itou, Hiroi Oka, Takuya Nakajo, Yuichi Yato
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Publication number: 20130009300Abstract: A dug portion (50) in which a die-bonding material is filled is provided to a lower surface of a stamping nozzle (42) used in a step of applying the die-bonding material onto a chip mounting portion of a wiring board. Planar dimensions of the dug portion (50) are smaller than external dimensions of a chip to be mounted on the chip mounting portion. In addition, a depth of the dug portion (50) is smaller than a thickness of the chip. When the thickness of the chip is 100 ?m or smaller, a problem of crawling up of the die-bonding material to an upper surface of the chip is avoided by applying the die-bonding material onto the chip mounting portion using the stamping nozzle (42).Type: ApplicationFiled: March 31, 2010Publication date: January 10, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yuichi Yato, Hiroi Oka