Patents by Inventor Hiroji Kawai
Hiroji Kawai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120404Abstract: This normally-off mode polarization super junction GaN-based field effect transistor has an undoped GaN layer 11, an AlxGa1-xN layer 12 (0<x<1), an island-like undoped GaN layer 13, a p-type GaN layer 14, a p-type InyGa1-yN layer 15 (0<y<1), a gate electrode 16 on the p-type InyGa1-yN layer 15 and a source electrode 17 and a drain electrode 17 on the AlxGa1-xN layer 12. When the polarization charge amount of the hetero-interface between the AlxGa1-xN layer 12 and the undoped GaN layer 11 and the hetero-interface between the AlxGa1-xN layer 12 and the undoped GaN layer 13 is denoted as NPZ and the thickness of the AlxGa1-xN layer 12 is denoted as d, NPZ d?2.64×1014 [cm?2 nm] is satisfied.Type: ApplicationFiled: October 5, 2021Publication date: April 11, 2024Inventors: Hiroji KAWAI, Shuichi YAGI, Hironobu NARUI
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Publication number: 20230352573Abstract: A semiconductor element includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a first intermediate layer, a second intermediate layer, a source electrode, a drain electrode, and a gate electrode. The band gap of the second semiconductor layer is larger than the band gaps of the first semiconductor layer and the third semiconductor layer. The band gaps of the first intermediate layer and the second intermediate layer that sandwich the second semiconductor layer are larger than the band gap of the second semiconductor layer.Type: ApplicationFiled: July 6, 2023Publication date: November 2, 2023Inventors: Hisao SATO, Koji OKUNO, Daisuke SHINODA, Toshiya UEMURA, Hironobu NARUI, Hiroji KAWAI, Shuichi YAGI
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Publication number: 20230170407Abstract: This normally-off mode polarization super junction GaN-based FET has an undoped GaN layer 11, an AlxGa1-xN layer 12, an island-like undoped GaN layer 13, a p-type GaN layer 14 and a p-type InyGa1-yN layer 15 which are stacked in order. The FET has a gate electrode 16 on the uppermost layer, a source electrode 17 and a drain electrode 17 on the AlxGa1-xN layer 12 and a p-type InzGa1-zN layer 19 and a gate electrode 20 which are located beside one end of the undoped GaN layer 13 on the AlxGa1-xN layer 12. The gate electrode 20 may be provided on the p-type InzGa1-zN layer 19 via a gate insulating film.Type: ApplicationFiled: September 16, 2021Publication date: June 1, 2023Inventors: Hiroji KAWAI, Shuichi YAGI, Hironobu NARUI
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Publication number: 20220238728Abstract: This diode is configured by a double gate PSJ-GaN-based FET. This FET has a GaN layer 11, an AlxGa1-xN layer 12, an undoped GaN layer 13, and a p-type GaN layer 14. A source electrode 19 and a drain electrode 20 are provided on the AlxGa1-xN layer 12, a first gate electrode 15 is provided on the p-type GaN layer 14, and a second gate electrode 18 is provided on a gate insulating film 17 provided inside a groove 16 which is provided in the AlxGa1-xN layer 12 between the source electrode 19 and the undoped GaN layer 13. The source electrode 19, the first gate electrode 15, and the second gate electrode 18 are connected to each other. Or the source electrode 19 and the second gate electrode 18 are connected to each other, and a positive voltage is applied to the first gate electrode 15 for the source electrode 19 and the second gate el electrode 18.Type: ApplicationFiled: March 5, 2020Publication date: July 28, 2022Inventors: Hiroji KAWAI, Shuichi YAGI, Takeru SAITO, Fumihiko NAKAMURA, Hironobu NARUI
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Publication number: 20200185930Abstract: According to the present invention, a quick charging control means is provided with a power semiconductor which comprises a sapphire substrate and a gallium nitride power transistor that is formed on the sapphire substrate; and a heat dissipation means, which dissipates heat generated during the electric power conversion in the quick charging control means, is bonded to the element outer surface of the gallium nitride power transistor. In one embodiment of the present invention, the power semiconductor employs polarization super junction. In another embodiment of the present invention, the heat dissipation means is connected to at least one of a source region and a drain region in the element outer surface of the gallium nitride power transistor, and extends in the direction away from the sapphire substrate.Type: ApplicationFiled: November 14, 2017Publication date: June 11, 2020Inventors: Tsutomu Kuwata, Teruo Ogawa, Hiroji Kawai, Tomio Sugano
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Patent number: 10014399Abstract: This hetero-junction bipolar transistor includes a first n-type GaN layer, an AlxGa1-xN layer (0.1?x?0.5), an undoped GaN layer having a thickness of not less than 20 nm, a Mg-doped p-type GaN layer having a thickness of not less than 100 nm, and a second n-type GaN layer which are sequentially stacked. The first n-type GaN layer and the AlxGa1-xN layer form an emitter, the undoped GaN layer and the p-type GaN layer form a base, and the second n-type GaN layer forms a collector. During non-operation, two-dimensional hole gas is formed in a part of the undoped GaN layer near the hetero interface between the AlxGa1-xN layer and the undoped GaN layer. When the thickness of the p-type GaN layer is b [nm], the hole concentration of the p-type GaN layer is p [cm?3], and the concentration of the two-dimensional hole gas is Ps [cm?2], p×b×10?7+Ps?1×1013 [cm?2] is satisfied.Type: GrantFiled: February 3, 2017Date of Patent: July 3, 2018Assignee: Powdec K.K.Inventor: Hiroji Kawai
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Publication number: 20180175182Abstract: This hetero-junction bipolar transistor includes a first n-type GaN layer, an AlxGa1-xN layer (0.1?x?0.5), an undoped GaN layer having a thickness of not less than 20 nm, a Mg-doped p-type GaN layer having a thickness of not less than 100 nm, and a second n-type GaN layer which are sequentially stacked. The first n-type GaN layer and the AlxGa1-xN layer form an emitter, the undoped GaN layer and the p-type GaN layer form a base, and the second n-type GaN layer forms a collector. During non-operation, two-dimensional hole gas is formed in a part of the undoped GaN layer near the hetero interface between the AlxGa1-xN layer and the undoped GaN layer. When the thickness of the p-type GaN layer is b [nm], the hole concentration of the p-type GaN layer is p [cm?3], and the concentration of the two-dimensional hole gas is Ps [cm?2], p×b×10?7+Ps?1×1013 [cm?2] is satisfied.Type: ApplicationFiled: February 3, 2017Publication date: June 21, 2018Inventor: Hiroji KAWAI
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Patent number: 9991335Abstract: Provided are a semiconductor device and a bidirectional field effect transistor which can easily overcome the tradeoff relation between the high voltage resistance and high speed in the semiconductor device using a polarization super junction, realize both the high voltage resistance and elimination of the occurrence of current collapse, operate at a high speed, and further the loss is low. The semiconductor device comprises a polarization super junction region and a p-electrode contact region. The polarization super junction region comprises an undoped GaN layer 11, an undoped AlxGa1-xN layer 12 with a thickness not smaller than 25 nm and not larger than 47 nm and 0.17?x?0.35, an undoped GaN layer 13 and a p-type GaN layer 14. When the reduced thickness tR is defined as tR=u+v(1+w×10?18) for the thickness u [nm] of the undoped GaN layer 13, the thickness v [nm] and the Mg concentration w [cm?3] of the p-type GaN layer 14, tR?0.864/(x?0.134)+46.0 [nm] is satisfied.Type: GrantFiled: November 18, 2014Date of Patent: June 5, 2018Assignee: POWDEC K.K.Inventors: Shoko Echigoya, Fumihiko Nakamura, Shuichi Yagi, Souta Matsumoto, Hiroji Kawai
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Publication number: 20170263710Abstract: Provided is a semiconductor element in which a two-dimensional hole gas with an enough concentration can exist, even though the p-type GaN layer is not provided on the topmost surface of the polarization super junction region. The semiconductor element comprises a polarization super junction region comprising an undoped GaN layer 11 with a thickness a [nm] (a is not smaller than 10 nm and not larger than 1000 nm), an AlxGa1-xN layer 12 and an undoped GaN layer 13. The Al composition x and the thickness t [nm] of the AlxGa1-xN layer 12 satisfy the following equation t??(a)x?(a) Where ? is expressed as Log (?)=p0+p1 log (a)+p2{log (a)}2 (p0=7.3295, p1=?3.5599, p2=0.6912) and ? is expressed as ?=p?0+p?1 log (a)+p?2{log (a)}2 (p?0=?3.6509, p?1=1.9445, p?2=?0.3793).Type: ApplicationFiled: November 5, 2015Publication date: September 14, 2017Applicant: POWDEC K.K.Inventors: Souta MATSUMOTO, Shoko ECHIGOYA, Shuichi YAGI, Fumihiko NAKAMURA, Hiroji KAWAI
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Publication number: 20160093691Abstract: Provided are a semiconductor device and a bidirectional field effect transistor which can easily overcome the tradeoff relation between the high voltage resistance and high speed in the semiconductor device using a polarization super junction, realize both the high voltage resistance and elimination of the occurrence of current collapse, operate at a high speed, and further the loss is low. The semiconductor device comprises a polarization super junction region and a p-electrode contact region. The polarization super junction region comprises an undoped GaN layer 11, an undoped AlxGa1-xN layer 12 with a thickness not smaller than 25 nm and not larger than 47 nm and 0.17?x?0.35, an undoped GaN layer 13 and a p-type GaN layer 14. When the reduced thickness tR is defined as tR=u+v(1+w×10?18) for the thickness u [nm] of the undoped GaN layer 13, the thickness v [nm] and the Mg concentration w [cm?3] of the p-type GaN layer 14, tR?0.864/(x?0.134)+46.0 [nm] is satisfied.Type: ApplicationFiled: November 18, 2014Publication date: March 31, 2016Inventors: Shoko ECHIGOYA, Fumihiko NAKAMURA, Shuichi YAGI, Souta MATSUMOTO, Hiroji KAWAI
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Patent number: 8785976Abstract: A low-loss GaN-based semiconductor device is provided. The semiconductor device has the InzGa1-zN layer (where 0?z<1), the AlxGa1-xN layer (where 0<x<1), the InyGa1-yN layer (where 0?y<1) and the p-type InwGa1-wN layer (where 0?w<1) which are sequentially stacked on a base substrate of a C-plane sapphire substrate, etc. At a non-operating time, the two-dimensional hole gas is formed in the InyGa1-yN layer in the vicinity part of a hetero-interface between the AlxGa1-xN layer and the InyGa1-yN layer, and the two-dimensional electron gas is formed in the InzGa1-zN layer in the vicinity part of a hetero-interface between the InzGa1-zN layer and the AlxGa1-xN layer.Type: GrantFiled: June 21, 2011Date of Patent: July 22, 2014Assignees: The University of Sheffield, Powdec K.K.Inventors: Akira Nakajima, Sankara Narayanan Ekkanath Madathil, Yasunobu Sumida, Hiroji Kawai
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Publication number: 20130126942Abstract: A low-loss GaN-based semiconductor device is provided. The semiconductor device has the InzGa1-zN layer (where 0?z<1), the AlxGa1-xN layer (where 0<x<1), the InyGa1-yN layer (where 0?y<1) and the p-type InwGa1-wN layer (where 0?w<1) which are sequentially stacked on a base substrate of a C-plane sapphire substrate, etc. At a non-operating time, the two-dimensional hole gas 15 is formed in the InyGa1-yN layer in the vicinity part of a hetero-interface between the AlxGa1-xN layer and the InyGa1-yN layer, and the two-dimensional electron gases is formed in the InzGa1-zN layer in the vicinity part of a hetero-interface between the InzGa1-zN layer and the AlxGa1-xN layer.Type: ApplicationFiled: June 21, 2011Publication date: May 23, 2013Applicants: POWDEC K.K., THE UNIVERSITY OF SHEFFIELDInventors: Akira Nakajima, Sankara Narayanan Ekkanath Madathil, Yasunobu Sumida, Hiroji Kawai
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Publication number: 20120280363Abstract: The method for manufacturing a semiconductor device comprises steps of: forming a growth mask with a plurality of openings directly or indirectly upon a substrate that comprises a material differing from GaN-based semiconductor; and growing a plurality of island-like GaN-based semiconductor layers upon the substrate using the growth mask in the (0001) plane orientation in a manner such that the 1-100 direction extends in a direction parallel to the striped openings of the growth mask.Type: ApplicationFiled: August 17, 2010Publication date: November 8, 2012Applicant: POWDEC K. K.Inventors: Yasunobu Sumida, Shoko Hirata, Takayuki Inada, Shuichi Yagi, Hiroji Kawai
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Patent number: 6903392Abstract: A semiconductor device having a single-crystal substrate made of a material different from nitride III-V compound semiconductors, and a device made on one major surface of said single-crystal substrate by using III-V compound semiconductors, including electrical connection to said device being made through a via hole formed in said single-crystal substrate and method of making the same.Type: GrantFiled: January 24, 2001Date of Patent: June 7, 2005Assignee: Sony CorporationInventor: Hiroji Kawai
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Publication number: 20050087751Abstract: Disclosed herein is an insulating nitride layer suitable for group III-V nitride semiconductor devices. It has a high resistance and good insulating properties and hence it electrically isolates elements, without the active layer decreasing in conductivity. Disclosed also herein is a process for forming said nitride layer and a semiconductor device having said nitride layer for improved characteristic properties. The semiconductor device is an AlGaN/GaN HEMT or the like which has a GaN active layer and an insulating nitride layer formed thereon from a group III-V nitride compound semiconductor heavily doped mostly with a group IIB element (particularly Zn) in an amount not less than 1×1017/cm3.Type: ApplicationFiled: November 16, 2004Publication date: April 28, 2005Inventors: Fumihiko Nakamura, Hisayoshi Kuramochi, Hiroji Kawai
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Patent number: 6750481Abstract: A semiconductor crystal layer composed of GaN is grown on a base substrate composed of sapphire sandwiching a separating layer composed of AlN and a buffer layer composed of GaN. The separating layers and the buffer layers are distributed in the form of lines, and a flow-through hole for an etchant is formed in the side of these layers sandwiching an anti-growing film composed of SiO2. Thus, the etchant flows through the flow-through hole, the anti-growing film and the separating layer are etched, and the base substrate is easily isolated.Type: GrantFiled: March 15, 2002Date of Patent: June 15, 2004Assignee: Sony CorporationInventor: Hiroji Kawai
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Patent number: 6501154Abstract: There are provided a semiconductor substrate and a semiconductor laser using the semiconductor substrate which promises smooth and optically excellent cleaved surfaces and is suitable for fabricating semiconductor lasers using nitride III-V compound semiconductors. Using a semiconductor substrate, such as GaN substrate, having a major surface substantially normal to a {0001}-oriented face, e.g. {01-10}-oriented face or {11-20}-oriented face, or offset within ±5° from these faces, nitride III-V compound semiconductor layers are epitaxially grown on the substrate to form a laser structure. To make cavity edges, the GaN substrate is cleaved together with the overlying III-V compound semiconductor layers along high-cleavable {0001}-oriented faces.Type: GrantFiled: June 2, 1998Date of Patent: December 31, 2002Assignee: Sony CorporationInventors: Etsuo Morita, Masao Ikeda, Hiroji Kawai
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Patent number: 6468902Abstract: After making a GaN FET by growing GaN semiconductor layers on the surface of a sapphire substrate, the bottom surface of the sapphire substrate is processed by lapping, using an abrasive liquid containing a diamond granular abrasive material and reducing the grain size of the abrasive material in some steps, to reduce the thickness of the sapphire substrate to 100 &mgr;m or less. Thereafter, the bottom surface of the sapphire substrate is processed by etching using an etchant of phosphoric acid or phosphoric acid/sulfuric acid mixed liquid to remove a strained layer by lapping followed by making a via hole by etching the bottom surface of the sapphire substrate by using a similar etchant.Type: GrantFiled: January 24, 2001Date of Patent: October 22, 2002Assignee: Sony CorporationInventor: Hiroji Kawai
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Patent number: 6426264Abstract: A semiconductor crystal layer composed of GaN is grown on a base substrate composed of sapphire sandwiching a separating layer composed of AlN and a buffer layer composed of GaN. The separating layers and the buffer layers are distributed in the form of lines, and a flow-through hole for an etchant is formed in the side of these layers sandwiching an anti-growing film composed of SiO2. Thus, the etchant flows through the flow-through hole, the anti-growing film and the separating layer are etched, and the base substrate is easily isolated.Type: GrantFiled: January 14, 2000Date of Patent: July 30, 2002Assignee: Sony CorporationInventor: Hiroji Kawai
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Patent number: RE38613Abstract: A new and improved method for growing a p-type nitride III-V compound semiconductor is provided which can produce a p-type nitride compound semiconductors having a high carrier concentration, without the need for annealing to activate impurities after growth. In a preferred embodiment, a p-type nitride compound semiconductor, such as p-type GaN, is grown by metal organic chemical vapor deposition methods using a nitrogen source material which does not release hydrogen during release of nitrogen and the semiconductor is grown in an inactive gas. The nitrogen source materials may be selected from nitrogen compounds that contain hydrogen radicals groups and alkyl radicals groups and/or phenyl radicals groups provided that the total amount of hydrogen radicals groups is less than or equal to the sum total of alkyl radicals groups and phenyl radicals groups present in the nitrogen compound used as the nitrogen source material.Type: GrantFiled: September 18, 2002Date of Patent: October 5, 2004Assignee: Sony CorporationInventors: Hiroji Kawai, Tsunenori Asatsuma, Fumihiko Nakamura