Patents by Inventor Hirokazu Kami
Hirokazu Kami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8516414Abstract: A behavioral synthesis device include a profile unit that implements an electronic circuit at a reconfigurable hardware based on a first register transfer level description generated by a behavioral synthesis unit, actuates the implemented electronic circuit, and causes the electric circuit to output profile information from the actuated electronic circuit; and an optimizer that generates optimization information for optimizing a behavioral synthesis carried out by the behavioral synthesis unit based on the profile information that the profile unit causes the electric circuit to output, and outputs the generated optimization information to the behavioral synthesis unit, wherein the behavioral synthesis unit acquires a first behavioral level description, and subjects the acquired first behavioral level description to behavioral synthesis and generates the second register transfer level description based on the optimization information outputted by the optimizer.Type: GrantFiled: March 24, 2009Date of Patent: August 20, 2013Assignee: NEC CorporationInventors: Yoshinosuke Kato, Takao Toi, Noritsugu Nakamura, Toru Awashima, Hirokazu Kami
-
Patent number: 7793092Abstract: Configuration codes for implementing a plurality of circuits having different attributes are generated and stored in a memory for each task executed in a reconfigurable device. When the reconfigurable device is operated, an appropriate circuit to be executed by the reconfigurable device is selected in accordance with an operation state of the system from among a plurality of circuits having different attributes, and the configuration code for implementing the selected circuit is loaded from the memory into the reconfigurable device.Type: GrantFiled: December 27, 2006Date of Patent: September 7, 2010Assignees: NEC Corporation, NEC Electronics CorporationInventors: Takao Toi, Tooru Awashima, Hirokazu Kami, Takeshi Inuo, Nobuki Kajihara, Taro Fujii, Kenichiro Anjo, Koichiro Furuta, Masato Motomura
-
Patent number: 7650484Abstract: An array-type computer processor including a data path unit communicating with a state control unit obtains data of a predetermined number of cooperative partial instruction codes, and operates with temporarily holding only a predetermined number of data-obtained instruction codes comprising cooperative partial instruction codes corresponding to contexts and operation states for the data path unit and the state control unit, respectively, from an external program memory which stores data of a computer program.Type: GrantFiled: February 3, 2005Date of Patent: January 19, 2010Assignees: NEC Corporation, NEC Electronics CorporationInventors: Takeshi Inuo, Nobuki Kajihara, Takao Toi, Tooru Awashima, Hirokazu Kami, Taro Fujii, Kenichiro Anjo, Kouichiro Furuta, Masato Motomura
-
Patent number: 7647485Abstract: A data processing device for debugging code for a parallel arithmetic device that includes a plurality of data processing circuits arranged in a matrix and that causes, for each operating cycle, successive transitions of operation states in accordance with object code includes: operation execution means for causing the parallel arithmetic device to execute state transitions by means of the object code; device halt means for temporarily halting the state transitions for each operating cycle; a result output means for reading and supplying as output at least a portion of held data, connection relations, and operation commands of the plurality of data processing circuits of the halted parallel arithmetic device; a resume input means for receiving as input a resume command of the state transitions; and an operation resumption means for causing the operation execution means to resume the state transitions upon input of a resume command.Type: GrantFiled: August 27, 2004Date of Patent: January 12, 2010Assignees: NEC Corporation, NEC Electronics CorporationInventors: Hirokazu Kami, Takao Toi, Toru Awashima, Kenichiro Anjo, Koichiro Furuta, Taro Fujii, Masato Motomura
-
Publication number: 20090249262Abstract: A behavioral synthesis device include a profile unit that implements an electronic circuit at a reconfigurable hardware based on a first register transfer level description generated by a behavioral synthesis unit, actuates the implemented electronic circuit, and causes the electric circuit to output profile information from the actuated electronic circuit; and an optimizer that generates optimization information for optimizing a behavioral synthesis carried out by the behavioral synthesis unit based on the profile information that the profile unit causes the electric circuit to output, and outputs the generated optimization information to the behavioral synthesis unit, wherein the behavioral synthesis unit acquires a first behavioral level description, and subjects the acquired first behavioral level description to behavioral synthesis and generates the second register transfer level description based on the optimization information outputted by the optimizer.Type: ApplicationFiled: March 24, 2009Publication date: October 1, 2009Inventors: Yoshinosuke Kato, Takao Toi, Noritsugu Nakamura, Toru Awashima, Hirokazu Kami
-
Publication number: 20080040700Abstract: The liveness information that is obtained from behavioral synthesis and that shows the periods during which variables described in a behavioral level description have valid values is used for processing at a logic synthesizing stage, placement and routing stage, debugging stage, writing stage of circuit information to a reconfigurable device, or the like, so as to use storage elements that are to be allocated to the variables described in the behavioral level description in common and to achieve optimization such as minimizing data paths and the like. Also in a debugger and in a writing device for writing circuit information, the aforementioned liveness information is used to execute a task of not displaying invalid variables, a task of reducing the amount of information to be saved to an external memory, etc.Type: ApplicationFiled: March 29, 2007Publication date: February 14, 2008Applicant: NEC CORPORATIONInventors: Yoshinosuke Katoh, Toru Awashima, Noritsugu Nakamura, Hirokazu Kami, Takao Toi
-
Patent number: 7287146Abstract: An array-type computer processor stops, with a plurality of computer programs held, a state control unit and a data-path unit, upon input of event data for task switching. The array-type computer processor obtains the operation state of the state control unit and the processed data of the data-path unit when stopped, and temporarily holds them for each of a plurality of the computer programs. Upon completion of this, the array-type computer processor reads the operation state and processed data of any other computer program and sets them in the state control unit and data-path unit. Upon completion of this, the array-type computer processor outputs to the state control unit the event data for starting the operation. The state control unit then starts to sequentially transfer the operation state, thereby making it possible to perform the process operations according to a plurality of computer programs in a time-sharing manner.Type: GrantFiled: February 2, 2005Date of Patent: October 23, 2007Assignees: NEC Corporation, NEC Electronics CorporationInventors: Takeshi Inuo, Nobuki Kajihara, Takao Toi, Tooru Awashima, Hirokazu Kami, Taro Fujii, Kenichiro Anjo, Kouichiro Furuta, Masato Motomura
-
Publication number: 20070150718Abstract: Configuration codes for implementing a plurality of circuits having different attributes are generated and stored in a memory for each task executed in a reconfigurable device. When the reconfigurable device is operated, an appropriate circuit to be executed by the reconfigurable device is selected in accordance with an operation state of the system from among a plurality of circuits having different attributes, and the configuration code for implementing the selected circuit is loaded from the memory into the reconfigurable device.Type: ApplicationFiled: December 27, 2006Publication date: June 28, 2007Applicants: NEC CORPORATION, NEC ELECTRONICS CORPORATIONInventors: Takao Toi, Tooru Awashima, Hirokazu Kami, Takeshi Inuo, Nobuki Kajihara, Taro Fujii, Kenichiro Anjo, Koichiro Furuta, Masato Motomura
-
Publication number: 20050172103Abstract: An array-type computer processor obtains data of a predetermined number of cooperative partial instruction codes, and operates with temporarily holding only a predetermined number of data-obtained instruction codes, from an external program memory which stores data of a computer program. Every time the operations with the temporarily-held instruction codes are complete, the subsequent instruction codes are data obtained, so that the operation according to a computer program can be performed even if the data volume of the computer program is over the storage capacity.Type: ApplicationFiled: February 3, 2005Publication date: August 4, 2005Inventors: Takeshi Inuo, Nobuki Kajihara, Takao Toi, Tooru Awashima, Hirokazu Kami, Taro Fujii, Kenichiro Anjo, Kouichiro Furuta, Masato Motomura
-
Publication number: 20050172102Abstract: An array-type computer processor stops, with a plurality of computer programs held, a state control unit and a data-path unit, upon input of event data for task switching. The array-type computer processor obtains the operation state of the state control unit and the processed data of the data-path unit when stopped, and temporarily holds them for each of a plurality of the computer programs. Upon completion of this, the array-type computer processor reads the operation state and processed data of any other computer program and sets them in the state control unit and data-path unit. Upon completion of this, the array-type computer processor outputs to the state control unit the event data for starting the operation. The state control unit then starts to sequentially transfer the operation state, thereby making it possible to perform the process operations according to a plurality of computer programs in a time-sharing manner.Type: ApplicationFiled: February 2, 2005Publication date: August 4, 2005Inventors: Takeshi Inuo, Nobuki Kajihara, Takao Toi, Tooru Awashima, Hirokazu Kami, Taro Fujii, Kenichiro Anjo, Kouichiro Furuta, Masato Motomura
-
Publication number: 20050050522Abstract: A data processing device for debugging code for a parallel arithmetic device that includes a plurality of data processing circuits arranged in a matrix and that causes, for each operating cycle, successive transitions of operation states in accordance with object code includes: operation execution means for causing the parallel arithmetic device to execute state transitions by means of the object code; device halt means for temporarily halting the state transitions for each operating cycle; a result output means for reading and supplying as output at least a portion of held data, connection relations, and operation commands of the plurality of data processing circuits of the halted parallel arithmetic device; a resume input means for receiving as input a resume command of the state transitions; and an operation resumption means for causing the operation execution means to resume the state transitions upon input of a resume command.Type: ApplicationFiled: August 27, 2004Publication date: March 3, 2005Inventors: Hirokazu Kami, Takao Toi, Toru Awashima, Kenichiro Anjo, Koichiro Furuta, Taro Fujii, Masato Motomura