Patents by Inventor Hirokazu Tokuno
Hirokazu Tokuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8614475Abstract: A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids.Type: GrantFiled: December 31, 2012Date of Patent: December 24, 2013Assignees: Spansion LLC, Advanced Mirco Devices, Inc.Inventors: Minh Van Ngo, Hirokazu Tokuno, Angela T. Hui, Wenmei Li, Hsiao-Han Thio
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Patent number: 8415256Abstract: During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a layer of low deposition temperature gap-fill dielectric into a high aspect ratio opening, such as a shallow trench or a gap between closely spaced apart gate electrode structures, as at a thickness of about 10 ? to about 500 ?, curing after deposition, as by UV radiation or by heating at a temperature of about 400° C. to about 1000° C., depositing another layer of low deposition temperature gap-filled dielectric, and curing after deposition. Embodiments include separately depositing and separately curing multiple layers.Type: GrantFiled: December 30, 2010Date of Patent: April 9, 2013Inventors: Alexander Nickel, Lu You, Hirokazu Tokuno, Minh Tran, Minh Van Ngo, Hieu Pham, Erik Wilson, Robert Huertas
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Patent number: 8367493Abstract: A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids.Type: GrantFiled: April 20, 2005Date of Patent: February 5, 2013Assignees: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Minh Van Ngo, Hirokazu Tokuno, Angela T. Hui, Wenmei Li, Hsiao-Han Thio
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Patent number: 8309457Abstract: A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).Type: GrantFiled: October 27, 2011Date of Patent: November 13, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Kouros Ghandehari, Anna M. Minvielle, Marina V. Plat, Hirokazu Tokuno
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Publication number: 20120045888Abstract: A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).Type: ApplicationFiled: October 27, 2011Publication date: February 23, 2012Inventors: Kouros Ghandehari, Anna M. Minvielle, Marina V. Plat, Hirokazu Tokuno
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Patent number: 8048797Abstract: A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).Type: GrantFiled: May 19, 2009Date of Patent: November 1, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Kouros Ghandehari, Anna M. Minvielle, Marina V. Plat, Hirokazu Tokuno
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Patent number: 8026169Abstract: Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing the generation and/or diffusion of hydrogen ions during back end processing, such as annealing inlaid Cu. Embodiments include annealing inlaid Cu in an N2 atmosphere containing low H2 or no H2, and at temperatures less than 200° C., e.g., 100° C. to 150° C.Type: GrantFiled: November 6, 2006Date of Patent: September 27, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Lu You, Alexander Nickel, Minh Q. Tran, Minh-Van Ngo, Hieu Pham, Erik Wilson, Hirokazu Tokuno, Amir Hossein Jafarpour, Inkuk Kang, Robert Huertas
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Patent number: 7927723Abstract: A film stack includes an interlayer dielectric formed over one or more devices. The film stack further includes a first layer having a high extinction coefficient formed on the interlayer dielectric and a second layer having a low extinction coefficient formed on the first layer. The first and second layers prevent ultraviolet induced damage to the one or more devices while minimizing reflectivity for lithographic processes.Type: GrantFiled: March 29, 2005Date of Patent: April 19, 2011Assignees: Spansion LLC, GlobalFoundries Inc.Inventors: Angela T. Hui, Ning Cheng, Minh Van Ngo, Hirokazu Tokuno, Wenmei Li
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Patent number: 7888269Abstract: A method includes forming a layer of silicon oxynitride (SiON), silicon rich nitride (SiRN) or silicon nitride (Si3N4) over a layer of semiconducting material. The method further includes forming a first layer of anti-reflective material over the layer of SiON, SiRN or Si3N4 and forming a second layer of anti-reflective material over the first layer. The method also includes using the first layer, second layer and layer of SiON, SiRN or Si3N4 as a mask when etching a pattern in the layer of semiconducting material.Type: GrantFiled: October 24, 2005Date of Patent: February 15, 2011Assignees: Spansion LLC, GlobalFoundries, Inc.Inventors: Kouros Ghandehari, Hirokazu Tokuno, David Matsumoto, Christopher H. Raeder, Christopher Foster, Weidong Qian, Minh Van Ngo
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Patent number: 7884030Abstract: During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a layer of low deposition temperature gap-fill dielectric into a high aspect ratio opening, such as a shallow trench or a gap between closely spaced apart gate electrode structures, as at a thickness of about 10 ? to about 500 ?, curing after deposition, as by UV radiation or by heating at a temperature of about 400° C. to about 1000° C., depositing another layer of low deposition temperature gap-filled dielectric, and curing after deposition. Embodiments include separately depositing and separately curing multiple layers.Type: GrantFiled: April 21, 2006Date of Patent: February 8, 2011Assignee: Advanced Micro Devices, Inc. and Spansion LLCInventors: Alexander Nickel, Lu You, Hirokazu Tokuno, Minh Tran, Minh Van Ngo, Hieu Pham, Erik Wilson, Robert Huertas
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Publication number: 20100009536Abstract: A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).Type: ApplicationFiled: May 19, 2009Publication date: January 14, 2010Inventors: Kouros Ghandehari, Anna M. Minvielle, Marina V. Plat, Hirokazu Tokuno
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Patent number: 7538026Abstract: A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).Type: GrantFiled: April 4, 2005Date of Patent: May 26, 2009Assignee: Advanced Micro Devices, Inc.Inventors: Kouros Ghandehari, Anna M. Minvielle, Marina V. Plat, Hirokazu Tokuno
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Patent number: 7534732Abstract: Cu interconnects are formed with composite capping layers for reduced electromigration, improved adhesion between Cu and the capping layer, and reduced charge loss in associated non-volatile transistors. Embodiments include depositing a first relatively thin silicon nitride layer having a relatively high concentration of Si—H bonds on the upper surface of a layer of Cu for improved adhesion and reduced electromigration, and depositing a second relatively thick silicon nitride layer having a relatively low concentration of Si—H bonds on the first silicon nitride layer for reduced charge loss.Type: GrantFiled: February 17, 2006Date of Patent: May 19, 2009Assignees: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Minh Van Ngo, Erik Wilson, Hieu Pham, Robert Huertas, Lu You, Hirokazu Tokuno, Alexander Nickel, Minh Tran
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Publication number: 20080108193Abstract: Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing the generation and/or diffusion of hydrogen ions during back end processing, such as annealing inlaid Cu. Embodiments include annealing inlaid Cu in an N2 atmosphere containing low H2 or no H2, and at temperatures less than 200° C., e.g., 100° C. to 150° C.Type: ApplicationFiled: November 6, 2006Publication date: May 8, 2008Inventors: Lu You, Alexander Nickel, Minh Q. Tran, Minh-Van Ngo, Hieu Pham, Erik Wilson, Hirokazu Tokuno, Amir Hossein Jafarpour, Inkuk Kang, Robert Huertas
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Publication number: 20080096364Abstract: Gap filling between features which are closely spaced is significantly improved by initially depositing a thin conformal layer followed by depositing a layer of gap filling dielectric material. Embodiments include depositing a thin conformal layer of silicon nitride or silicon oxide, as by atomic layer deposition or pulsed layer deposition, into the gap between adjacent gate electrode structures such that it flows into undercut regions of dielectric spacers on side surfaces of the gate electrode structures, and then depositing a layer of BPSG or P-HDP oxide on the thin conformal layer into the gap. Embodiments further include depositing the layers at a temperature less than 430° C., as by depositing a P-HDP oxide after depositing the conformal liner when the gate electrode structures include a layer of nickel silicide.Type: ApplicationFiled: October 18, 2006Publication date: April 24, 2008Inventors: Erik Wilson, Minh-Van Ngo, Hieu Pham, Robert Huertas, Lu You, Hirokazu Tokuno, Alexander Nickel, Minh Tran
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Patent number: 7341956Abstract: A method includes forming a group of disposable hard mask structures on a semiconductor device that includes a group of memory cells. The method further includes using the disposable hard mask structures to precisely control a junction profile of the memory cells.Type: GrantFiled: April 7, 2005Date of Patent: March 11, 2008Assignees: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Hirokazu Tokuno, Minh-Van Ngo, Angela T. Hui, Cinti Xiaohua Chen
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Patent number: 7307027Abstract: A method of forming a dielectric between memory cells in a device includes forming multiple memory cells, where a gap is formed between each of the multiple memory cells. The method further includes performing a high density plasma deposition (HDP) process to fill at least a portion of the gap between each of the multiple memory cells with a dielectric material.Type: GrantFiled: August 11, 2005Date of Patent: December 11, 2007Assignees: Advanced Micro Devices, Inc., Spansion LLCInventors: Minh Van Ngo, Alexander Nickel, Hieu Pham, Jean Yang, Hirokazu Tokuno, Weidong Qian
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Patent number: 7238571Abstract: A memory device may include a number of memory cells, a first interlayer dielectric formed over the memory cells and at least one metal layer formed over the interlayer dielectric. A dielectric layer may be formed over the metal layer. The dielectric layer may represent a cap layer formed at or near an upper surface of the memory device and may be deposited at a relatively low temperature.Type: GrantFiled: February 24, 2005Date of Patent: July 3, 2007Assignees: Advanced Micro Devices, Inc., Spansion LLCInventors: Hirokazu Tokuno, Wenmei Li, Ning Cheng, Minh Van Ngo, Angela T. Hui, Cinti X. Chen
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Patent number: 7220643Abstract: A method for forming a memory device is provided. A memory cell stack is formed over a substrate. The memory cell stack includes a first layer formed over the substrate and a second layer formed over the first layer. A dielectric layer is formed over the first and second layers and the substrate. The dielectric layer is etched to expose at least an upper surface of the memory cell stack. The second layer is etched to recess the second layer with respect to an upper surface of the dielectric layer. A silicide region is formed on the second layer in the memory cell stack, where the silicide region in each memory cell stack is bounded by the dielectric layer extending above the upper surface of the memory cell stack.Type: GrantFiled: June 8, 2005Date of Patent: May 22, 2007Assignee: Spansion LLCInventors: Hajime Wada, Jaeyong Park, Hirokazu Tokuno, Rinji Sugino
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Publication number: 20070093070Abstract: A method includes forming a layer of silicon oxynitride (SiON), silicon rich nitride (SiRN) or silicon nitride (Si3N4) over a layer of semiconducting material. The method further includes forming a first layer of anti-reflective material over the layer of SiON, SiRN or Si3N4 and forming a second layer of anti-reflective material over the first layer. The method also includes using the first layer, second layer and layer of SiON, SiRN or Si3N4 as a mask when etching a pattern in the layer of semiconducting material.Type: ApplicationFiled: October 24, 2005Publication date: April 26, 2007Inventors: Kouros Ghandehari, Hirokazu Tokuno, David Matsumoto, Christopher Raeder, Christopher Foster, Weidong Qian, Minh Ngo