Abstract: In one aspect of this invention, a receiver sequentially demodulates sequentially received burst signals into original digital data signals. A data extraction unit extracts base station information from the digital data signals sequentially demodulated by the receiver. A level detector detects the signal levels of received signals containing the burst signals sequentially received by the receiver. A control unit causes a display unit to display the signal levels detected by the level detector in accordance with elapse of the reception time, and display the base station information extracted by the data extraction unit. In another aspect of this invention, a determination unit quantitatively determines errors of the burst signals from the digital data signals sequentially demodulated by the receiver, and outputs the determination results concerning the validity of the digital data contained in the burst signals.

Abstract: A rational frequency division device eliminates spurious components by a simple arrangement and can set a broad frequency modulation range. A frequency synthesizer using the rational frequency division device includes an arithmetic circuit, which outputs the frequency division ratio to a frequency divider in a PLL circuit constituted by a variable frequency oscillator 4, a frequency divider 6, and a phase detector 2. The arithmetic circuit includes a plurality of series-connected cumulative adders 22 which include a first cumulative adder that receives a rational number defined by an integer value and a decimal value, an integer value extraction circuit 23 for extracting an integer value from the output value of the cumulative adder of the final stage, and a delay circuit 24 for outputting the integer value extracted by the integer value extraction circuit to the frequency divider as the frequency division ratio, and outputting the integer value to the respective cumulative adders as a feedback value.