Abstract: A semiconductor device having a circuit that selectively adjusts an impedance of an output buffer. A calibration operation can be performed automatically without issuing a calibration command from a controller. Because a calibration operation to a memory is performed in response to an auto refresh command having been issued for a predetermined number of times, a periodic calibration operation can be secured, and a read operation or a write operation is not requested from a controller during a calibration operation. A start-up circuit activates the calibration circuit when a refresh counter indicates a predetermined value, and prohibits a refresh operation in response to the auto refresh command when the calibration circuit is activated. A temperature detecting circuit may be used to change the frequency of performing a calibration operation.

Abstract: A display device includes a liquid crystal display panel 5, a touch panel 3 that is disposed on a display surface side of the liquid crystal display panel 5 and that has a touch operation area wider than a display area of the above-mentioned liquid crystal display panel 5, and a guard 4 or 4a that is disposed between an area 3a included in the touch operation area and corresponding to the display area, and an area 3b included in the touch operation area and corresponding to an outside of the display area, and that physically restricts an operation object which performs an operation on the above-mentioned touch operation area from moving between the areas.

Abstract: A semiconductor memory disclosed in this disclosure includes first and second memory cell arrays, a first main data line that transfers the read data read from the first memory cell array, a second main data line that transfers the read data read from the second memory cell array, a main amplifier coupled to the second main data line, and a repeater circuit coupled to the first main data line and the second main data line.

Abstract: An information apparatus includes a liquid crystal display unit 6; a touch panel 3 that is mounted on the display surface of the liquid crystal display unit 6, that has a touch operation area wider than the display area of the liquid crystal display unit 6, and that has a specific operation handling section 3b which is formed on an area corresponding to an extra-display area of the touch operation area and which accepts an operation for a specific operation item of an information apparatus 1; a controller 7 that carries out control in a manner that causes the specific operation handling section 3b to accept an operation corresponding to a specific operation item of external equipment 2.

Abstract: A display device includes a touch panel 3 that has a touch operation area wider than an image display area, an operation member formed in an area 3b, other than the image display area, in the touch operation area, and an operation feeling generator 7 that provides an operation feeling for a pointing object which has operated the operation member.

Abstract: A data transfer operation completion detection circuit including a first counter for performing a shifting operation in response to the generation of a read initiation signal, a second counter for performing a shifting operation in response to the generation of a burst completion signal, and an SR latch circuit for generating a read enable signal in response to the burst completion signal being generated when the count value of the first counter matches the count value of the second counter. The completion of a read operation or another data transfer operation is thus detected based on a read initiation signal reception history; therefore, it is possible to detect whether all read operations are complete at a given time even if a new read command is received while a read operation or the like is in progress.

Abstract: A device includes an output circuit, a DLL (Delay Locked Loop) circuit including a first delay line receiving a first clock signal and outputting, in response to receiving the clock signal, a second clock signal supplied to the output circuit, and an ODT (On Die Termination) circuit receiving an ODT activation signal and outputting, in response to receiving the ODT activation signal, an ODT output signal supplied to the output circuit to set the output circuit in a resistance termination state, and the ODT circuit including a second delay line configured to be set by the DLL circuit in an equivalent delay amount that is equivalent to a delay amount of the first delay line, the ODT output signal being, in a first time-period during which the ODT activation signal is in an active state, generated by being conveyed via the second delay line in which the equivalent delay amount has been set.

Abstract: Disclosed herein is a semiconductor device that includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command; and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. The second control circuit sets the cycle to a first cycle until executing the refresh operation to all the memory groups after receiving the first refresh command, and the second control circuit sets the cycle to a second cycle that is longer than the first cycle after executing the refresh operation to all the memory groups.

Abstract: A device includes a first power supply line supplying a first voltage, first, second, and third nodes, a selection circuit connected between the first power supply line and the first node, a first anti-fuse connected between the first node and the second node, and a second anti-fuse connected between the first node and the third node. The second node and the third node are not connected to each other.

Abstract: A semiconductor device according to this invention includes a first power line that supplies power to a first circuit, a second power line that supplies power to a second circuit, and a capacitive element that is provided between the first power line and the second power line.

Abstract: A semiconductor chip includes: a data output buffer that outputs a data signal; a first power-supply pad that supplies a first power-supply potential to the data output buffer; a power-supply wiring that is connected to the first power-supply pad; a strobe output buffer that outputs a strobe signal; and a second power-supply pad that supplies a second power-supply potential to the strobe output buffer. The power-supply wiring and the second power-supply pad are electrically independent of each other. Therefore, the power-supply noise associated with the switching of the data output buffer does not spread to the strobe output buffer. Thus, it is possible to improve the quality of the strobe signal.

Abstract: A semiconductor device is disclosed. A first power supply wiring for connecting between a first output circuit consisting of a predetermined number of output circuits and a first power supply pad which corresponds to the first output circuit, is connected via a resistor with a second power supply wiring for connecting between a second output circuit consisting of a predetermined number of output circuit and a second power supply pad which corresponds to the second output circuit. Thus, power supply noise that is to be propagated to certain output circuits via in-chip output power supply wirings can be reduced.

Abstract: A method for controlling termination impedance of a data terminal in a dynamic random access memory device includes receiving a mode register set command to set an operation mode to a first mode, setting the operation mode in a mode register to the first mode, receiving a self-refresh entry command, entering self-refresh mode, activating a first input buffer connected to a termination impedance control terminal, and receiving an impedance control signal at the first buffer, wherein the termination impedance of the data terminal is set to a first impedance value if the termination impedance control signal has a first level and the termination impedance of the data terminal is set to a second impedance value if the termination impedance control signal has a second level.

Abstract: A semiconductor device according to this invention includes a first power line that supplies power to a first circuit, a second power line that supplies power to a second circuit, and a capacitive element that is provided between the first power line and the second power line.

Abstract: Disclosed herein is an information processing system having first and second devices. The second device alternately issues a self-refresh command and a self-refresh exit command to the first device. The first device performs a refresh operation once in response to the self-refresh command and updates a state of a DLL circuit in response to the self-refresh exit command.

Abstract: A data transfer operation completion detection circuit including a first counter for performing a shifting operation in response to the generation of a read initiation signal, a second counter for performing a shifting operation in response to the generation of a burst completion signal, and an SR latch circuit for generating a read enable signal in response to the burst completion signal being generated when the count value of the first counter matches the count value of the second counter. The completion of a read operation or another data transfer operation is thus detected based on a read initiation signal reception history; therefore, it is possible to detect whether all read operations are complete at a given time even if a new read command is received while a read operation or the like is in progress.

Abstract: Disclosed herein is a semiconductor device having a self-refresh mode in which a refresh operation of the storage data is performed. The semiconductor device activates an input buffer circuit that receives an impedance control command to control an impedance of the data terminal even in the self-refresh mode so that the semiconductor device can change an impedance of the data terminal during the self-refresh mode.

Abstract: Disclosed herein is a semiconductor device having first and second operation modes. In the first operation mode, the semiconductor device deactivates a DLL circuit during a self-refresh mode. In the second operation mode, the semiconductor device intermittently activates the DLL circuit to generate an internal clock signal.

Abstract: A method for operating a dynamic random access memory device includes providing a clock signal to a clock terminal of the dynamic random access memory device, selecting one of a first operating mode and a second operating mode of the dynamic random access memory device, the first operating mode, when selected, corresponding to the DRAM periodically refreshing a first number of word lines, and the second operating mode, when selected, corresponding to the DRAM periodically refreshing a second number of word lines different from the first number, and providing a self-refresh command to a command terminal of the dynamic random access memory device.

Abstract: Disclosed herein is an information processing system having first and second devices. The second device alternately issues a self-refresh command and a self-refresh exit command to the first device. The first device performs a refresh operation once in response to the self-refresh command and updates a state of a DLL circuit in response to the self-refresh exit command.