Abstract: An MOS-type solid-state imaging apparatus includes unit cells arranged in a two-dimensional matrix, each unit cell being constituted by a photodiode, an amplification transistor having a gate to which an output from the photodiode is input, a vertical selection transistor connected in series with the amplification transistor, and a reset transistor connected between the drain and gate of the amplification transistor to discharge the signal from the photodiode, a plurality of vertical address lines connected to the gates of the vertical selection transistors and arranged in a row direction, a vertical address circuit for driving the vertical address lines, a plurality of vertical signal lines arranged in a column direction in which currents are read out from the amplification transistors, a plurality of load transistors each connected to one end of a corresponding one of the vertical signal lines, a plurality of horizontal selection transistors each connected to the other end of a corresponding one of the vert

Abstract: An instruction decoder decodes an instruction code, whereupon immediate data, if included, is searched to see whether it is encoded or not. After decoding, an operation code in the instruction code is informed to the execution unit. If the instruction code includes immediate data, the data is transmitted to a data decoder to be decoded according to a given rule. The decoded data is transmitted to the execution unit. Because the immediate data is reduced in size through encoding, the number of times instructions are fetched is accordingly reduced, which resultantly increases processing efficiency. Since an entire instruction code is also reduced in size, a wider variety of operations are instructed using the same instruction code format.

Abstract: A measuring method and a measuring apparatus for accurately measuring an initial imbalance deviating from a predetermined imbalance, when the predetermined imbalance is to be left in a body of rotation.

Abstract: A clock control method is proposed, in which malfunctions caused by clock skews are decreased when the same high-speed clock is used inside and outside an IC. An original clock is input via CKIN, with the return path of an output buffer connected to an input buffer in an input/output buffer. The clock, once output via the output buffer, returns to the IC as a reentry clock. The selected reentry clock or original clock are used in the IC. The clock appearing at SYSCK is used in an external circuit. By using the reentry clock in the IC, the clock skew corresponding to the delay of the output buffer can be decreased.

Abstract: An MOS-type solid-state imaging apparatus includes an imaging region formed by two-dimensionally arranging unit cells serving as photoelectric conversion portions on a semiconductor substrate, a plurality of vertical address lines arranged in a row direction of the imaging region to select a row of unit cells to be addressed, a plurality of vertical signal lines arranged in a column direction of the imaging region to read out signals from the unit cells in each column, a plurality of load transistors each connected to one end of each of the vertical signal lines, and a plurality of horizontal selection transistors each connected to the other end of each of the vertical signal lines.

Abstract: Disclosed is a program execution device capable of carrying out high-speed computation with a low amount of hardware and small program size, while permitting future expansion of the range of functions. General-purpose registers R0˜R4 are virtual registers and a specific computation is related to read/write processing to and from each of these registers R0˜R4. When instruction decoder 3 has decoded an instruction, if it has been determined that the instruction is a data transfer instruction denoting access to any one of the general-purpose registers R0˜4, the computation related to the register to be accessed is carried out. A expanded range of computation types can be related to different general-purpose registers.

Abstract: A group of registers 26 consists of a plurality of general-purpose registers R0, R1, . . . . A flag is provided for each of these general-purpose registers. When data to be written to, for instance, general-purpose register R0 is zero, the register flag is set in conjunction with the data writing. Thereafter, it is possible to determine with a conditional branching instruction if the general-purpose register R0 data is zero by looking at the flag, and there is no need to read out data and perform a computation.

Abstract: An MOS-type solid-state imaging apparatus includes an imaging region formed by two-dimensionally arranging unit cells serving as photoelectric conversion portions on a semiconductor substrate, a plurality of vertical address lines arranged in a row direction of the imaging region to select a row of unit cells to be addressed, a plurality of vertical signal lines arranged in a column direction of the imaging region to read out signals from the unit cells in each column, a plurality of load transistors each connected to one end of each of the vertical signal lines, and a plurality of horizontal selection transistors each connected to the other end of each of the vertical signal lines.

Abstract: A method and an apparatus for generating information input which are capable of realizing a direct command type information input scheme by which the gesture or the motion can be inputted easily. The apparatus has a timing signal generation unit for generating a timing signal; a lighting unit for emitting a light whose intensity vary in time, according to the timing signal generated by the timing signal generation unit; and a reflected light extraction unit having a sensor array for detecting a reflected light from a target object resulting from the light emitted by the lighting unit, in synchronization with the timing signal generated by the timing signal generation unit, so as to obtain a spatial intensity distribution of the reflected light in a form of a reflected light image indicative of an information input related to the target object, in separation from an external light that is illuminating the target object.

Abstract: In an MOS-type solid-state imaging apparatus, plural unit cells are arranged in a two-dimensional matrix, unit cells in one horizontal line (row) are selected by a vertical address circuit, and vertical signal lines to which outputs from the unit cells in one vertical line (column) are supplied are selected by a horizontal address circuit, thereby sequentially outputting signals from the respective unit cells. Each unit cell includes an output circuit for outputting an output from a photodiode to a vertical signal line, photodiodes connected in parallel to the output circuit, and a selection switch for selecting one of the photodiodes and connecting it to the output circuit. The output circuit comprising an amplification transistor for amplifying an output from the photodiode, a selection transistor for selecting the unit cell, and a reset transistor for resetting the charge in the photodiode.

Abstract: A processor that executes an instruction stream having at least one compressed register field allows for smaller programs and greater processing speed. The instructions have at least one n-bit register number field and at least one m-bit register code field, where n is less than m. The n-bit register number field is capable of designating any register in a set of working registers. The m-bit register code field is capable of designating any register of a subset of the working registers. The m-bit register code may designate a source or destination register of the current instruction, a source or destination register of the last instruction, or a destination register of the second to last instruction. An instruction fetch section of the processor fetches the instruction words from memory.

Abstract: An instruction fetcher reads out instructions and data from a memory. The instructions and data are decoded by an instruction decoder. When a data transfer instruction is fed to an input register in a register section, a second execution unit starts an execution, the execution result being then stored in an output register. If any unprocessed data remains in the input or output register, the subsequent data processing is suspended. Input and output register sets and execution sub-units may be provided such that any of these components can be selected depending on the necessary process. Since a given execution is executed by the data transfer instruction, the data can be processed at high speed through a simplified program. Since no specific and additional computation instruction is required, the expandability can be improved.

Abstract: A data driven data processing apparatus executes a data flow graph as a program for a plurality of processing elements arranged in a pipeline ring for transferring packets of scalar and vector operation data. An execution circuit on the pipeline ring controls execution of scalar and vector operations by separate scalar and vector operation circuits. The execution circuit has a single arithmetic logic circuit that performs both the scalar and vector operations, preferably processing in a time-shared, parallel manner.

Abstract: A processor uses a special instruction set to enhance exception handling, such as interrupt handling. The processor uses a pipeline comprising five separate stages of fetch, decode, execute, memory access and register write. For each operation executed by the processor, the operation has an operation initiation instruction and an operation result fetch instruction, each of which has multiple stages. The operation result fetch instruction awaits the completion of the operation initiation instruction. While waiting, the operation result fetch instruction is suspended, preferably before any hardware resource is changed, and if necessary canceled to accommodate an exception handling signal. Since the hardware resource is changed at the "execute" stage of the operation, the operation result fetch instruction is suspended at the "decode" stage. Upon receiving the exception handling signal, the operation result fetch instruction may be canceled and the processor is free to process the exception handling.

Abstract: A parallel computer system includes a plurality of processing elements each comprising a network control unit. The network control unit of the processing element has ports to north, east, west and south, and row directional communication lines and column directional communication lines are connected to each port forming a taurus mesh network. Each processing element operates in two communication control modes, in a bi-directional communication mode or in a unidirectional communication mode. In the bi-directional communication mode, the network control unit permits eastward and westward transmission of data through the row directional communication lines and northward and southward transmission of data through the column directional communication lines.

Abstract: A second execution unit such as a coprocessor incorporated into a processor is connected such that the direction of its processing flow is opposite to that of the main pipeline processing flow, and executes high-speed multiplication operations and specific operations. Conventionally, the second execution unit has been provided in the same direction as a first execution unit. With this prior art arrangement, the second execution unit is initiated at an early stage of pipeline processing. With the arrangement of this invention, the second execution unit is initiated at a later stage, giving sufficient time before all the operation data are prepared. Thus, it is unnecessary for the apparatus to start subsequent processing until all operation data become available, thereby enhancing processing performance.

Abstract: In a method of manufacturing magnetic recording medium, the position and operating condition and the like of an orienting device are determined so that a solvent weight ratio X satisfies 0.7.ltoreq.X.ltoreq.1.0.

Abstract: An instruction decoder decodes an instruction code, whereupon immediate data, if included, is searched to see whether it is encoded or not. After decoding, an operation code in the instruction code is informed to the execution unit. If the instruction code includes immediate data, the data is transmitted to a data decoder to be decoded according to a given rule. The decoded data is transmitted to the execution unit. Because the immediate data is reduced in size through encoding, the number of times instructions are fetched is accordingly reduced, which resultantly increases processing efficiency. Since an entire instruction code is also reduced in size, a wider variety of operations are instructed using the same instruction code format.

Abstract: A parallel computer system includes a plurality of processing elements each including a network control unit and a data processing unit. The network control unit of each processing element includes a north, east, west and south ports to each of which a row and column communication lines are connected so as to construct a torus mesh network. A specific mode flag which is set by a reset signal from a host computer coupled to the network and a number register are formed in the data processing unit. If a packet is sent to the network from the host computer when the specific mode flag is set, in the processing element which received the packet, the processing element number included in the packet is set in the number register and the specific mode flag is reset so that the processing element can be identified by that processing element number in a normal mode.

Abstract: A parallel computer system includes a plurality of processing elements each comprising a network control unit. The network control unit of the processing element has ports to north, east, west and south, and row directional communication lines and column directional communication lines are connected to each port forming a taurus mesh network. Each processing element operates in two communication control modes, in a bi-directional communication mode or in a unidirectional communication mode. In the bi-directional communication mode, the network control unit permits eastward and westward transmission of data through the row directional communication lines and northward and southward transmission of data through the column directional communication lines.