Patents by Inventor Hiroki Otsuki

Hiroki Otsuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240089588
    Abstract: The imaging method is used in an imaging apparatus including an imaging element that captures a subject image and a moving mechanism configured to change a relative position between the subject image and the imaging element, the imaging method including: a changing step of changing the relative position a plurality of times; an imaging step of acquiring a plurality of first images by capturing the subject image using the imaging element at a plurality of the relative positions; a combining step of generating a second image by combining the plurality of first images; and a display step of performing a temporal display relating to the imaging step or the combining step.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: FUJIFILM Corporation
    Inventors: Kosuke TAKAHASHI, Koichi TANAKA, Shunsuke MIYAGISHIMA, Hiroki SAITO, Tomoki OTSUKI
  • Patent number: 8368782
    Abstract: An image pickup apparatus includes a frame operation unit configured to perform addition to or subtraction from a frame and a storage unit configured to store a result of an operation performed by the frame operation unit. A data bus including two channels, one for writing to the storage unit and the other for reading from the storage unit, is provided between the frame operation unit and the storage unit.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: February 5, 2013
    Assignee: Sony Corporation
    Inventor: Hiroki Otsuki
  • Patent number: 7719593
    Abstract: An image processing apparatus for processing an image signal, including: an operation processing section performing an operation according to a detected value of the image signal; a latch signal generation section for generating a plurality of latch signals, which indicate a timing of processing for the operation processing section and are based on a plurality of different picture rates applied to the image signal; a latch signal selection section selecting one of the plurality of latch signals inputted from the latch signal generation section and outputting the selected latch signal to the operation processing section; and a latch signal selection indication section indicating to the latch signal selection section a latch signal to be selected from the plurality of latch signals.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: May 18, 2010
    Assignee: Sony Corporation
    Inventors: Ting Zhang, Hiroki Otsuki
  • Publication number: 20100053374
    Abstract: An image pickup apparatus includes a frame operation unit configured to perform addition to or subtraction from a frame and a storage unit configured to store a result of an operation performed by the frame operation unit. A data bus including two channels, one for writing to the storage unit and the other for reading from the storage unit, is provided between the frame operation unit and the storage unit.
    Type: Application
    Filed: July 14, 2009
    Publication date: March 4, 2010
    Applicant: Sony Corporation
    Inventor: Hiroki OTSUKI
  • Publication number: 20080278609
    Abstract: An imaging apparatus includes a defective pixel storing unit to store positional information of a defective pixel among pixels in an imaging device and pixel defect information indicating whether a defective pixel group including defective pixels includes the defective pixel related to the positional information; an image input unit to input an image; a defective pixel determining unit to determine whether each pixel in the input image is a defective pixel; a pixel sharing defect determining unit to determine whether the defective pixel is included in the defective pixel group; a pixel type determining unit to determine the type of each pixel in the input image; an interpolated pixel selecting unit to select surrounding pixels of the defective pixel; an interpolation value calculating unit to calculate an interpolation value of the defective pixel; and an interpolation value substituting unit to substitute the value of the defective pixel with the interpolation value.
    Type: Application
    Filed: May 2, 2008
    Publication date: November 13, 2008
    Applicant: Sony Corporation
    Inventor: Hiroki Otsuki
  • Publication number: 20060262195
    Abstract: An image processing apparatus for processing an image signal, including: an operation processing section performing an operation according to a detected value of the image signal; a latch signal generation section for generating a plurality of latch signals, which indicate a timing of processing for the operation processing section and are based on a plurality of different picture rates applied to the image signal; a latch signal selection section selecting one of the plurality of latch signals inputted from the latch signal generation section and outputting the selected latch signal to the operation processing section; and a latch signal selection indication section indicating to the latch signal selection section a latch signal to be selected from the plurality of latch signals.
    Type: Application
    Filed: May 1, 2006
    Publication date: November 23, 2006
    Applicant: Sony Corporation
    Inventors: Ting Zhang, Hiroki Otsuki
  • Publication number: 20030088840
    Abstract: The processing quantity of each description part is estimated through a source code analysis of a system operation description language or through simulation, or power consumption of each function is estimated through an operation description analysis of functions. Predetermined threshold values are set with respect to the processing quantity and the power consumption of each description part or function, so as to determine S/W and H/W implementation, and then, S/W and H/W partitioning is carried out. Thereafter, it is determined whether or not the total processing quantity or the total power consumption satisfies a desired design condition. Also, the S/W and H/W partitioning can be adjusted again in comprehensive consideration of the power consumption and the processing quantity, and the accuracy in the S/W and H/W partitioning can be improved by providing an instruction set simulator with a function to analyze power consumption.
    Type: Application
    Filed: December 23, 2002
    Publication date: May 8, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Tomonori Yonezawa, Takayuki Sasaki, Takahiro Kondo, Hiroki Otsuki, Tsuyoshi Nakamura
  • Patent number: 6513146
    Abstract: The processing quantity of each description part is estimated through a source code analysis of a system operation description language or through simulation, or power consumption of each function is estimated through an operation description analysis of functions. Predetermined threshold values are set with respect to the processing quantity and the power consumption of each description part or function, so as to determine S/W and H/W implementation, and then, S/W and H/W partitioning is carried out. Thereafter, it is determined whether or not the total processing quantity or the total power consumption satisfies a desired design condition. Also, the S/W and H/W partitioning can be adjusted again in comprehensive consideration of the power consumption and the processing quantity, and the accuracy in the S/W and H/W partitioning can be improved by providing an instruction set simulator with a function to analyze power consumption.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: January 28, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tomonori Yonezawa, Takayuki Sasaki, Takahiro Kondo, Hiroki Otsuki, Tsuyoshi Nakamura