Patents by Inventor Hiroki Yarimizu

Hiroki Yarimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100122072
    Abstract: A debugging system according to an exemplary embodiment of the present invention includes: a plurality of arithmetic processing units (51, 52) that perform arithmetic processing; a comparison unit (53) that compares outputs from the plurality of arithmetic processing units (51, 52); and a debug processing unit (54) that outputs a stop instruction for stopping operation of the comparison unit (53), to the comparison unit 53, when debug processing is performed on a predetermined arithmetic processing unit among the plurality of arithmetic processing units (51, 52).
    Type: Application
    Filed: September 22, 2009
    Publication date: May 13, 2010
    Applicant: NEC ELECTRONIC CORPORATION
    Inventor: Hiroki Yarimizu