Patents by Inventor Hiroko Douchi
Hiroko Douchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050242864Abstract: Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock.Type: ApplicationFiled: February 11, 2005Publication date: November 3, 2005Inventors: Kenichi Kawasaki, Yasuharu Sato, Terumasa Kitahara, Masao Nakano, Masao Taguchi, Yoshihiro Takemae, Yasurou Matsuzaki, Koichi Nishimura, Yoshinori Okajima, Naoharu Shinozaki, Hiroko Douchi
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Patent number: 6498524Abstract: Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock.Type: GrantFiled: November 7, 2000Date of Patent: December 24, 2002Assignee: Fujitsu LimitedInventors: Kenichi Kawasaki, Yasuharu Sato, Terumasa Kitahara, Masao Nakano, Masao Taguchi, Yoshihiro Takemae, Yasurou Matsuzaki, Koichi Nishimura, Yoshinori Okajima, Naoharu Shinozaki, Hiroko Douchi
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Patent number: 6466075Abstract: A clock signal generator which is particularly useful for a double data rate SDRAM (DDR-SDRAM) includes two or more clock signal input buffers and an enable signal input buffer. The clock signal generator generates internal clock signals that fluctuate at substantially different timings, yet the relationship between the internal clock signals with respect to validation and invalidation timing is constant. A latch circuit latches an enable signal from the enable signal buffer in accordance with a first internal clock signal from a first one of the clock signal buffers. A first enable signal connected to the latch circuit holds the latched enable signal in accordance with the first internal clock signal. A second enable circuit receives the first enable signal and the first internal clock signal and generates a second enable signal used to activate the clock signal buffers.Type: GrantFiled: April 5, 2001Date of Patent: October 15, 2002Assignee: Fujitsu LimitedInventors: Hiroko Douchi, Hiroyoshi Tomita
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Patent number: 6298004Abstract: Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock.Type: GrantFiled: July 15, 1997Date of Patent: October 2, 2001Assignee: Fujitsu LimitedInventors: Kenichi Kawasaki, Yasuharu Sato, Terumasa Kitahara, Masao Nakano, Masao Taguchi, Yoshihiro Takemae, Yasurou Matsuzaki, Koichi Nishimura, Yoshinori Okajima, Naoharu Shinozaki, Hiroko Douchi
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Patent number: 6275086Abstract: A clock signal generator which is particularly useful for a double data rate SDRAM (DDR-SDRAM) includes two or more clock signal input buffers and an enable signal input buffer. The clock signal generator generates internal clock signals that fluctuate at substantially different timings, yet the relationship between the internal clock signals with respect to validation and invalidation timing is constant. A latch circuit latches an enable signal from the enable signal buffer in accordance with a first internal clock signal from a first one of the clock signal buffers. A first enable signal connected to the latch circuit holds the latched enable signal in accordance with the first internal clock signal. A second enable circuit receives the first enable signal and the first internal clock signal and generates a second enable signal used to activate the clock signal buffers.Type: GrantFiled: August 27, 1999Date of Patent: August 14, 2001Assignee: Fujitsu LimitedInventors: Hiroko Douchi, Hiroyoshi Tomita
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Publication number: 20010011916Abstract: A clock signal generator which is particularly useful for a double data rate SDRAM (DDR-SDRAM) includes two or more clock signal input buffers and an enable signal input buffer. The clock signal generator generates internal clock signals that fluctuate at substantially different timings, yet the relationship between the internal clock signals with respect to validation and invalidation timing is constant. A latch circuit latches an enable signal from the enable signal buffer in accordance with a first internal clock signal from a first one of the clock signal buffers. A first enable signal connected to the latch circuit holds the latched enable signal in accordance with the first internal clock signal. A second enable circuit receives the first enable signal and the first internal clock signal and generates a second enable signal used to activate the clock signal buffers.Type: ApplicationFiled: April 5, 2001Publication date: August 9, 2001Applicant: Fujitsu LimitedInventors: Hiroko Douchi, Hiroyoshi Tomita
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Patent number: 6081142Abstract: A load adjusting circuit 36 adjusts the load value L=L2 of a dummy load circuit 31x corresponding to the outputs of a frequency determining circuit 37 and an interface determining circuit 35 as L2=L1-.DELTA.L holding, where L=L1 is a proper value in the case that the access time does not depend on the frequency of the data DQ and .DELTA.L corresponds to a half of the maximum value tlc of the deviation of the access time that varies corresponding to the frequency of the data DQ. A DLL circuit 40 delays a internal clock iCLK by a time .delta.tx so that a difference between phases of the clock iCLK and a dummy internal clock d.sub.-- iCLK becomes a predetermined value. The delay time .delta.tx is equal to a value determined in such a way that .delta.tx=67 tx0 is determined with activating the DLL circuit 40, tlc is determined and .delta.tx is finally determined as .delta.tx=.delta.tx0+ tlc/2 or .delta.tx=.delta.tx0-tlc/2 due to the condition of data frequency at determining .delta.tx0.Type: GrantFiled: March 19, 1998Date of Patent: June 27, 2000Assignee: Fujitsu LimitedInventors: Hiroko Douchi, Naoharu Shinozaki
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Patent number: 6023175Abstract: The present invention relates to a level interface circuit, which receives a first interface input signal having a level H and a level L, as fixed potentials, and a first reference level which is midway therebetween, and a second interface input signals having a level H, a level L and a second reference level determined in accordance with a power source voltage, and which compares an input signal of one of said first and second interface input with one of said first and second reference level signal and generates an output signal, said level interface circuit further comprising: a first and a second transistors, having a common source connection, for receiving said input signal and said reference level signal at respective gates; a current source transistor connected to said source of said first and said second transistors; a load circuit connected to drains of said first and said second transistors; a voltage control transistor provided between said load circuit and said power voltage source; and a voltage cType: GrantFiled: January 30, 1998Date of Patent: February 8, 2000Assignee: Fujitsu LimitedInventors: Kazuhiro Nunomiya, Toshiya Uchida, Hiroko Douchi