Patents by Inventor Hiroko Nakaso

Hiroko Nakaso has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11929972
    Abstract: An information processing method executed by a computer to control notification by a plurality of terminals (first terminal and second terminal) associated with an appliance includes: obtaining information defining, for each state of a plurality of possible states of the appliance, whether the state is a predetermined state that requires the notification by all of the first terminal and the second terminal; obtaining a state of the appliance; determining whether the state of the appliance obtained is the predetermined state; performing control to cause all of the first terminal and the second terminal to make the notification, when it is determined that the state of the appliance is the predetermined state; and performing control to cause a specific terminal out of the first terminal and the second terminal to make the notification, when it is determined that the state of the appliance is not the predetermined state.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: March 12, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masafumi Okubo, Mariko Nakaso, Hiroko Sugimoto
  • Patent number: 6782492
    Abstract: In a cluster computer which connects a plurality of nodes that include memory and processors through an interconnection network, shutting down of a node due to an irrecoverable error that occurs in a common communication area is prevented, and the availability of the cluster computer is increased. A system control apparatus in each node sends a system error stop notification to the memory access origin when an irrecoverable error occurred during a memory access request generated in one node is sent to the node proper memory located on the same node step (S 17). However, a common communication area error notification is sent to the memory access origin (step S 10 and step S 18), when an irrecoverable error occurs when a memory access request generated in one node is sent to the common communication area of the memory located on another node and when a memory access request generated on one node is sent to the common communication area of the memory of the same node, and the node shut down is prevented.
    Type: Grant
    Filed: November 4, 1999
    Date of Patent: August 24, 2004
    Assignee: NEC Corporation
    Inventor: Hiroko Nakaso