Patents by Inventor Hiromi Abe
Hiromi Abe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11986847Abstract: Described herein is a technique capable of properly attaching a nozzle to a reaction tube. According to one aspect thereof, there is provided a nozzle installation jig including: a lower plate configured to make contact with a process vessel in a vicinity of a lower end opening of the process vessel in which a nozzle is provided; a frame fixed to the lower plate and extending upward with respect to the lower plate; an upper plate fixed to the frame and provided with a sensor configured to detect a position of the nozzle in the process vessel; and a notification device configured to transmit a notification to an operator according to a detection result of the sensor.Type: GrantFiled: March 17, 2023Date of Patent: May 21, 2024Assignee: KOKUSAI ELECTRIC CORPORATIONInventors: Yoshitaka Abe, Nobuhito Shima, Hiromi Okada, Shinya Morita, Mamoru Ohishi
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Patent number: 11974447Abstract: A novel light-emitting device is provided. A light-emitting device with high emission efficiency is provided. A light-emitting device with a long lifetime is provided. A light-emitting device with low driving voltage is provided. The light-emitting device includes an anode, a cathode, and an EL layer between the anode and the cathode. The EL layer includes a hole-injection layer, a light-emitting layer, and an electron-transport layer. The hole-injection layer is positioned between the anode and the light-emitting layer. The electron-transport layer is positioned between the light-emitting layer and the cathode. The hole-injection layer contains a first substance and a second substance. The first substance is an organic compound which has a hole-transport property and a HOMO level higher than or equal to ?5.7 eV and lower than or equal to ?5.4 eV. The second substance exhibits an electron-accepting property with respect to the first substance.Type: GrantFiled: October 26, 2022Date of Patent: April 30, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satoshi Seo, Hiromi Seo, Kunihiko Suzuki, Kanta Abe, Yuji Iwaki, Naoaki Hashimoto, Tsunenori Suzuki
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Patent number: 11968889Abstract: A light-emitting element having a long lifetime is provided. A light-emitting element exhibiting high emission efficiency in a high luminance region is provided. A light-emitting element includes a light-emitting layer between a pair of electrodes. The light-emitting layer contains a first organic compound, a second organic compound, and a phosphorescent compound. The first organic compound is represented by a general formula (GO). The molecular weight of the first organic compound is greater than or equal to 500 and less than or equal to 2000. The second organic compound is a compound having an electron-transport property. In the general formula (GO), Ar1 and Ar2 each independently represent a fluorenyl group, a spirofluorenyl group, or a biphenyl group, and Ar3 represents a substituent including a carbazole skeleton.Type: GrantFiled: June 11, 2021Date of Patent: April 23, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takao Hamada, Hiromi Seo, Kanta Abe, Kyoko Takeda, Satoshi Seo
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Publication number: 20240116709Abstract: A substrate processing apparatus includes: a loading/unloading part having a first side surface into or from which a container accommodating a substrate is loaded or unloaded and a second side surface opposite to the first side surface; a substrate transfer part extending in a first direction orthogonal to the second side surface; and a plurality of batch processors adjacent to each other in a length direction of the substrate transfer part. The loading/unloading part includes: a first transfer device and a second transfer device configured to transfer the container; a first area accessible to the first transfer device and having a plurality of first storage shelves configured to store the container, a second area accessible to the second transfer device and having a plurality of second storage shelves configured to store the container; and a movable shelf configured to be movable between the first area and the second area.Type: ApplicationFiled: October 9, 2023Publication date: April 11, 2024Inventors: Masato KADOBE, Hiromi NITADORI, Takahiro ABE, Junichi SATO
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Patent number: 10566255Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.Type: GrantFiled: July 23, 2019Date of Patent: February 18, 2020Assignee: Renesas Electronics CorporationInventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
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Publication number: 20190348332Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.Type: ApplicationFiled: July 23, 2019Publication date: November 14, 2019Inventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
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Publication number: 20190057913Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.Type: ApplicationFiled: October 22, 2018Publication date: February 21, 2019Inventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
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Patent number: 10134648Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.Type: GrantFiled: January 22, 2018Date of Patent: November 20, 2018Assignee: Renesas Electronics CorporationInventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
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Publication number: 20180145001Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.Type: ApplicationFiled: January 22, 2018Publication date: May 24, 2018Inventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
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Patent number: 9911673Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.Type: GrantFiled: April 22, 2017Date of Patent: March 6, 2018Assignee: Renesas Electronics CorporationInventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
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Publication number: 20170229359Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.Type: ApplicationFiled: April 22, 2017Publication date: August 10, 2017Inventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
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Patent number: 9646901Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.Type: GrantFiled: July 25, 2016Date of Patent: May 9, 2017Assignee: Renesas Electronics CorporationInventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
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Publication number: 20160336244Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.Type: ApplicationFiled: July 25, 2016Publication date: November 17, 2016Inventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
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Publication number: 20160035636Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.Type: ApplicationFiled: October 6, 2015Publication date: February 4, 2016Inventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
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Patent number: 9165845Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.Type: GrantFiled: August 22, 2014Date of Patent: October 20, 2015Assignee: Renesas Electronics CorporationInventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
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Patent number: 8912540Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.Type: GrantFiled: March 13, 2013Date of Patent: December 16, 2014Assignee: Renesas Electronics CorporationsInventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
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Publication number: 20140361299Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.Type: ApplicationFiled: August 22, 2014Publication date: December 11, 2014Inventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
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Patent number: 8415199Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.Type: GrantFiled: December 2, 2011Date of Patent: April 9, 2013Assignee: Renesas Electronics CorporationInventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
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Publication number: 20120077310Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.Type: ApplicationFiled: December 2, 2011Publication date: March 29, 2012Inventors: Toshihiko AKIBA, Bunji Yasumura, Masanao Sato, Hiromi Abe
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Patent number: 8101433Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.Type: GrantFiled: March 30, 2009Date of Patent: January 24, 2012Assignee: Renesas Electronics CorporationInventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe