Patents by Inventor Hiromi Kusakabe

Hiromi Kusakabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4366448
    Abstract: A power-amplifying circuit embodying this invention includes a pre-amplifier stage which comprises two emitter-connected transitors, one of whose bases is supplied with an input signal and an output stage comprising complementary pair of a first transistor of a PNP type and an emitter-grounded second transistor of an NPN type which carry out a class-AB push-pull operation in accordance with the amplitude of a current from the pre-amplifier stage.
    Type: Grant
    Filed: March 26, 1980
    Date of Patent: December 28, 1982
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Hiromi Kusakabe, Masahide Nagumo
  • Patent number: 4357579
    Abstract: A power amplifier is supplied a DC power source voltage to its power-amplifying circuit from a switching regulator type DC power source. A driver circuit is supplied its DC power source voltage from a non-switching regulator type DC power source like a battery or a series regulator type DC power source, and the DC power source voltage for the driver circuit is limited to a level below the DC power source voltage for the power amplifying circuit to reduce or eliminate spurious emissions based on ripple voltage components on the signal supplied by the DC power source voltage.
    Type: Grant
    Filed: October 8, 1980
    Date of Patent: November 2, 1982
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Shuichi Kato, Hiromi Kusakabe, Hiroyasu Yamaguchi, Yoshihiro Yoshida
  • Patent number: 4292584
    Abstract: A constant current source circuit having a first diode connected transistor for providing a first potential, a second diode connected transistor and a first resistor connected in series with the second diode connected transistor for providing a second potential, a comparator compares the first potential with the second potential to provide a first current corresponding to the potential difference between the first and second potentials, third and fourth transistors which respond to the first current to bias the first and second transistors, and a constant current output circuit which responds the first current to provide a constant current output.
    Type: Grant
    Filed: June 4, 1979
    Date of Patent: September 29, 1981
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Hiromi Kusakabe
  • Patent number: 4282490
    Abstract: Disclosed is a demodulator circuit which comprises a limiter circuit, a differentiation circuit, a monostable multivibrator circuit and an integration circuit. The differentiation circuit is composed of a delay circuit and a differential logic circuit. The differentiation circuit supplies the monostable multivibrator circuit with a trigger pulse whose pulse width is determined by the delay circuit. The monostable multivibrator circuit is formed of a differential circuit, having a current source at its output circuit. The current source tends to increase the output voltage of the monostable multivibrator circuit and a driving impedance for the integration circuit.
    Type: Grant
    Filed: January 24, 1979
    Date of Patent: August 4, 1981
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Hiromi Kusakabe
  • Patent number: 4172238
    Abstract: A plurality of differential amplifier units are cascade connected into a plurality of stages. Odd numbered units except the last unit are double end units whereas even numbered units are single end units. Each unit comprises first and second transistors. The control electrode of at least one transistor of a succeeding unit is supplied with the output of a preceding unit. An input is applied to the control electrode of the first transistor of the first unit, through an external input terminal, and the control electrode of the second transistor of the first unit is grounded in the sense of alternating current through an external grounding terminal. The input terminal and the grounding terminal are interconnected through an impedance. The output of the last unit is fed back to the control electrodes of the second transistors of the odd numbered units.
    Type: Grant
    Filed: May 11, 1978
    Date of Patent: October 23, 1979
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventor: Hiromi Kusakabe
  • Patent number: 4117407
    Abstract: The frequency synthesizer tuner is constituted by a dynamic shift register including first and second shift registers connected in a loop, wherein an information is written into and read out of the dynamic shift register and circulated therethrough by clock pulses, an output circuit including a display unit and a frequency synthesizer to which the information read out of the first shift register is supplied through a latch circuit, and a memory circuit connected in parallel with the latch circuit, a transfer circuit connected between the first and second shift registers, a refresh circuit connected between the output circuit and the second shift register, and a keyboard and a keyboard input circuit for applying an input information to the first shift register.
    Type: Grant
    Filed: April 29, 1976
    Date of Patent: September 26, 1978
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventor: Hiromi Kusakabe