Abstract: The present invention provides a data processing device where a program can be commonly used and a vector table can be shared regardless of types of endian in a bi-endian system. An instruction is fixed to little endian, and endian of data to be used for executing the instruction is variable. A size of the respective vector addresses in the vector table is 32 bits, and the number of bits at the time of a data access is maximally 32 bits. A CPU fetches an instruction, and before the fetched instruction is executed, the CPU accesses to, for example, for 32-bit data in a memory. At this time, the CPU controls the aligner so that addresses and alignments of data to be stored in each address in byte unit in a data register are identical to addresses and alignments of data determined by little endian of an instruction without depending on types of the endian of the data.

Abstract: The present invention provides a data processing device where a program can be commonly used and a vector table can be shared regardless of types of endian in a bi-endian system. An instruction is fixed to little endian, and endian of data to be used for executing the instruction is variable. A size of the respective vector addresses in the vector table is 32 bits, and the number of bits at the time of a data access is maximally 32 bits. A CPU fetches an instruction, and before the fetched instruction is executed, the CPU accesses to, for example, for 32-bit data in a memory. At this time, the CPU controls the aligner so that addresses and alignments of data to be stored in each address in byte unit in a data register are identical to addresses and alignments of data determined by little endian of an instruction without depending on types of the endian of the data.

Abstract: In programming in high-level language, a method of generating a program supporting external specifications for generating secure codes having high tamper-resistance and automatically generating an executable program having tamper-resistance with regard to a portion designated by a user is provided. A syntax analysis step, an intermediate representation generation step, a register allocation step, an optimization processing step, an assembly language generation step, a machine language generation step and a machine language program linkage step are executed. And between finish of reading of the source program and generating the executable program, a tamper-resistant code insertion step of automatically generating a code having tamper-resistance coping with unjust analysis of an operation content of the executable program is executed to the source program, the intermediate representation, the assembly language program or the machine language program based on an instruction of a user.

Abstract: Disclosed here is a data processor provided with an addressing mode for calculating each effective address from the displacement (reference address) included in the subject instruction and the information retained in an index register allocated to a general-purpose register so as to minimize an increase of the logical/physical scale. The value in the index register is increased so as to be shifted according to the memory access size, for example, by one when the memory access size is byte and by two when the memory access size is word. Because both extension and shifting are included in the effective address calculation, the number of instructions, as well as the number of execution states are reduced. And, because the array size is smaller than the address space size, the upper part of each general-purpose register is used as a data register, thereby the data amount to be written in each general-purpose register is increased and the number of times for reading/writing from/in the subject memory is reduced.

Abstract: Expansion registers E0 to E7 are added to the existing general registers R0 to R7 built on-chip in a CPU 1 of 8 bits so that all the registers including the added expansion registers may be grasped in its entirety as address data to access to a memory or the like. The address operation is executed at a unit including both the expansion register and the corresponding general register. All the registers including the expansion registers are grasped as one unit of address data to handle the carry or borrow caused in the address operation. Since the expansion registers have their applications limited to the generation of address, the number of kinds or combinations of executable instructions is reduced without inviting a serious reduction in the data processing ability thereby to suppress the increase in the logical and physical scales of the CPU.The register is given 32 bits in its entirety by adding the expansion register Ei of 16 bits to the general registers RiH and RiL of 16 bits of the 8-bit CPU.

Abstract: Expansion registers E0 to E7 are added to the existing general registers R0 to R7 built on-chip in an 8-bit CPU (1) so that all the registers including the added expansion registers may be grasped in its entirety as address data to access to a memory or the like. The address operation is executed at a unit including both the expansion register and the corresponding general register. All the registers including the expansion registers are grasped as one unit of address data to handle the carry or borrow caused in the address operation. Since the expansion registers have their applications limited to the generation of address, the number of kinds or combinations of executable instructions is reduced without inviting a serious reduction in the data processing ability thereby to suppress the increase in the logical and physical scales of the CPU. The register is given 32 bits in its entirety by adding the expansion register Ei of 16 bits to the general registers RiH and RiL of 16 bits of the 8-bit CPU.

Abstract: A CPU has an upper compatibility with a low-order CPU to expand a continuously usable address space relatively. For latching data information, registers are constructed for being an address register with a bit number larger than the address bit number of a low-order CPU. The data information has its byte/word size specified by the size bit of an operation code. The utilization of the data information of a long word size is specified by either the prefix code or the operation code to which is newly added the same bit number as that of the low-order CPU. For the data information of the byte size, the high-/low-orders of the byte size register to be utilized are specified by predetermined 1 bit of a register specifying field. For the data information of the word size, the high-/low-orders of the word size register are specified by the predetermined 1 bit of that data information.

Abstract: This invention provides alginate oligosaccharides comprising calcium alginate oligosaccharide, which is obtained by treating potassium alginate and/or sodium alginate with a polysaccharide-decomposing enzyme (alginate lyase) produced by a microorganism and substituting potassium ion or sodium ion in the potassium alginate oligosaccharide or sodium alginate oligosaccharide thus obtained with calcium ion, and potassium-enriched potassium alginate oligosaccharide, which is obtained by substituting sodium ion in said oligosaccharide with potassium ion, and a method for producing the same. The present invention further provides a food which contains the above-mentioned alginate oligosaccharide and exhibits an antihypertensive action.

Abstract: This invention provides alginate oligosaccharides comprising calcium alginate oligosaccharide, which is obtained by treating potassium alginate and/or sodium alginate with a polysaccharide-decomposing enzyme (alginate lyase) produced by a microorganism and substituting potassium ion or sodium ion in the potassium alginate oligosaccharide or sodium alginate oligosaccharide thus obtained with calcium ion, and potassium-enriched potassium alginate oligosaccharide, which is obtained by substituting sodium ion in said oligosaccharide with potassium ion, and a method for producing the same. The present invention further provides a food which contains the above-mentioned alginate oligosaccharide and exhibits an antihypertensive action.

Abstract: This invention relates to a saturated polyester bottle-shaped container and a method of fabricating the same from a material such as polyethylene terephthalate incorporating high transparency and superior mechanical surface strength. The hard coating is formed by the steps of coating an ultraviolet curable coating of methyl methacrylate resin on the surface of the body and irradiating ultraviolet rays over the surface of the body coated with the hard coating. Thus, the bottle-shaped container can largely enhance the wear resistance and extreme smoothness of the surface to eliminate dirt adherence onto the surface. In a second embodiment, an ultraviolet ray curable coating is coated onto the bottle, followed by a transparent resin coating which is cross linked with the ultraviolet ray curable coating.