Patents by Inventor Hiromi Sakima

Hiromi Sakima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7481230
    Abstract: A plasma processing method allows to suppress the drop of the etching rate of the depoless-process without performing an additional seasoning process right after the dry cleaning process. The method includes a first and a second plasma processing step carried out in a single chamber and a step of dry cleaning an inside of the chamber by using a dummy substrate between the first and the second plasma processing step. Deposits are substantially accumulated in the chamber during the first plasma processing step, while substantially no deposits are accumulated in the chamber during the second plasma processing step. The dry cleaning step is performed by supplying into the chamber a deposit removing gas for removing the deposits produced in the chamber during the first plasma processing step and a dummy substrate etching gas capable of etching the dummy substrate.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: January 27, 2009
    Assignee: Tokyo Electron Limited
    Inventor: Hiromi Sakima
  • Publication number: 20040099634
    Abstract: A plasma processing method allows to suppress the drop of the etching rate of the depoless-process without performing an additional seasoning process right after the dry cleaning process. The method includes a first and a second plasma processing step carried out in a single chamber and a step of dry cleaning an inside of the chamber by using a dummy substrate between the first and the second plasma processing step. Deposits are substantially accumulated in the chamber during the first plasma processing step, while substantially no deposits are accumulated in the chamber during the second plasma processing step. The dry cleaning step is performed by supplying into the chamber a deposit removing gas for removing the deposits produced in the chamber during the first plasma processing step and a dummy substrate etching gas capable of etching the dummy substrate.
    Type: Application
    Filed: November 19, 2003
    Publication date: May 27, 2004
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Hiromi Sakima
  • Patent number: 6465359
    Abstract: A method and system for processing a substrate in the presence of high purity C5F8. When processing oxides and dielectrics in a gas plasma processing system, C5F8 is used in combination with a carrier gas (e.g., Ar) and one or more of CO and O2. When using a silicon nitride (SixNy) layer as an etch stop, effective etching is performed due to the selectivity of oxides versus silicon nitride. The method is used when etching down to self-aligning contacts and other layers. The method may be practiced with or without using an anti-reflective coating underneath the photoresist layer.
    Type: Grant
    Filed: September 17, 1999
    Date of Patent: October 15, 2002
    Assignee: Tokyo Electron Ltd.
    Inventors: Masahiro Yamada, Youbun Ito, Kouichiro Inazawa, Abron Toure, Kunihiko Hinata, Hiromi Sakima
  • Patent number: 6455411
    Abstract: A dual damascene process for low-k or ultra low-k dielectric such as organo-silicate glass (OSG). After the via (112) etch, a trench (121) is etched in the OSG layer (108) using a less-polymerizing fluorocarbon added to an etch chemistry comprising a fluorocarbon and low N2/Ar ratio. The low N2/Ar ratio controls ridge formation during the trench etch. The combination of a less-polymerizing fluorocarbon with a higher-polymerizing fluorocarbon achieves a high etch rate and defect-free conditions.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: September 24, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Ping Jiang, Francis G. Celii, Kenneth J. Newton, Hiromi Sakima
  • Publication number: 20020030174
    Abstract: A method and system for processing a substrate in the presence of high purity C5F8. When processing oxides and dielectrics in a gas plasma processing system, C5F8 is used in combination with a carrier gas (e.g., Ar) and one or more of CO and O2. When using a silicon nitride (SixNy) layer as an etch stop, effective etching is performed due to the selectivity of oxides versus silicon nitride. The method is used when etching down to self-aligning contacts and other layers. The method may be practiced with or without using an anti-reflective coating underneath the photoresist layer.
    Type: Application
    Filed: September 17, 1999
    Publication date: March 14, 2002
    Inventors: MASAHIRO YAMADA, YOUBUN ITO, KOUICHIRO INAZAWA, ABRON TOURE, KUNIHIKO HINATA, HIROMI SAKIMA
  • Publication number: 20020031906
    Abstract: A dual damascene process for low-k or ultra low-k dielectric such as organo-silicate glass (OSG). After the via (112) etch, a trench (121) is etched in the OSG layer (108) using a less-polymerizing fluorocarbon added to an etch chemistry comprising a fluorocarbon and low N2/Ar ratio. The low N2/Ar ratio controls ridge formation during the trench etch. The combination of a less-polymerizing fluorocarbon with a higher-polymerizing fluorocarbon achieves a high etch rate and defect-free conditions.
    Type: Application
    Filed: September 6, 2001
    Publication date: March 14, 2002
    Inventors: Ping Jiang, Francis G. Celii, Kenneth J. Newton, Hiromi Sakima
  • Patent number: 6159862
    Abstract: A method and system for processing a substrate in the presence of high purity C.sub.5 F.sub.8. When processing oxides and dielectrics in a gas plasma processing system, C.sub.5 F.sub.8 is used in combination with a carrier gas (e.g., Ar) and one or more of CO and O.sub.2. When using a silicon nitride (Si.sub.x N.sub.y) layer as an etch stop, effective etching is performed due to the selectivity of oxides versus silicon nitride. The method is used when etching down to self-aligning contacts and other layers. The method may be practiced with or without using an anti-reflective coating underneath the photoresist layer.
    Type: Grant
    Filed: June 1, 1998
    Date of Patent: December 12, 2000
    Assignee: Tokyo Electron Ltd.
    Inventors: Masahiro Yamada, Youbun Ito, Kouichiro Inazawa, Abron Toure, Kunihiko Hinata, Hiromi Sakima
  • Patent number: 5556500
    Abstract: An apparatus for etching a WSi film on a wafer by using a plasma of a gas containing a halogen element includes a vacuum process chamber in which upper and lower counter electrodes are provided. An electrostatic chuck is provided on a table at the center of a susceptor or the lower electrode. The wafer is held on the electrostatic chuck. A focus ring surrounding the wafer in a complementary manner is placed on a flange of the susceptor. The temperature of the wafer surface is set to be lower than that of the surface of the focus ring while the plasma is being generated. The focus ring comprises an inner part of amorphous carbon and an outer part of tungsten. While the plasma is being generated, a halide of tungsten generated from the outer part is diffused on the wafer surface, thereby correcting a distribution of the amount of the halide of tungsten on the wafer surface. Thus, the uniformity within the wafer surface of the etching rate and etching anisotropy is enhanced.
    Type: Grant
    Filed: March 3, 1995
    Date of Patent: September 17, 1996
    Assignees: Tokyo Electron Limited, Kabushiki Kaisha Toshiba
    Inventors: Makoto Hasegawa, Hiromi Sakima, Hiromitsu Kanbara, Yoshio Ishikawa, Yasuo Imamura, Makoto Aoki