Abstract: A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.

Abstract: A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.

Abstract: A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.

Abstract: A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.

Abstract: A display monitor apparatus has an analog signal input portion for receiving an analog video signal. a digital signal input portion for receiving a digital video signal, a detector portion for detecting a particular component included in the analog video signal, a first property data storage portion for storing a first set of property data used to control the display monitor apparatus to cope with the analog video signal, a second property data storage portion for storing a second set of property data used to control the display monitor apparatus to cope with the digital video signal, and a switch portion for choosing one of the first and second property data storage portions.

Abstract: A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.

Abstract: A semiconductor memory has a main memory and an ID memory, of which both store data in a nonvolatile memory. The data stored in the ID memory is compared with data entered from outside by a verifying circuit. Whether access to the main memory is permitted or not depends on the result of the verification by the verifying circuit. The operation code for accessing the ID memory is different from the operation code for accessing the main memory. The operation code for the ID memory is changed in accordance with the data stored in the ID memory.

Abstract: The same information is stored in two memory cells (26 and 26′) and the two memory cells are connected in parallel (OR) at a normal reading to synthesize an electric current in conformity with information in the two memory cells. Even if a floating gate and drain are shorted with each other in a storage transistor in one of the memory cells when a tunnel oxide film is deteriorated, destroyed or shorted by a high-tension stress, the discriminating voltage of a sense amplifier is determined so as to ensure normal reading of information in the other memory cell. The two memory cells are separated at test-reading for independent operations to ensure individual testing each memory cell.

Abstract: A non-volatile memory element, which includes a transistor and stores data by changing its threshold voltage, includes a semiconductor substrate, an electrically chargeable floating gate electrode layer above the main surface of the substrate, another electrically chargeable floating gate electrode layer above the main surface of the substrate, and a control gate electrode layer above these floating gate electrode layers, separated from them by an insulating film such that the voltage of the control gate electrode layer controls charged conditions of the floating gate electrode layers which are insulated from each other and disposed along the direction of the current flow in the transistor.

Abstract: A nonvolatile memory with a simple structure where recorded information can be read without destruction. A voltage is impressed between a control gate and a memory gate for writing. A ferroelectric layer is polarized in accordance with the direction of the impressed voltage. A control gate voltage to make channel is small when the ferroelectric layer is polarized with the control gate side being positive. Control gate voltage to make channel is large when the ferroelectric layer is polarized with the control gate side being negative. The reference voltage is impressed on the control gate for reading. A large drain current flows when the ferroelectric layer is polarized with a second polarization and a small drain current flows when the ferroelectric layer is polarized with a first polarization. Record information can be read by detecting the drain current. Polarization status of the ferroelectric is not destroyed in the reading operation.

Abstract: Nonvolatile memory with a simple structure where recorded information can be read without destruction: Voltage is impressed between control gate CG and memory gate MG at a writing operation. A ferroelectric layer 32 is polarized in accordance with the direction of the impressed voltage. The control gate voltage V.sub.CG to make a channel is low when the ferroelectric layer 32 is polarized with the control gate side being positive (polarized with second status). The control gate voltage V.sub.CG to make a channel is high when the ferroelectric layer 32 is polarized with the control gate side being negative (polarized with the first status). The reference voltage V.sub.ref is impressed to the control gate CG at the reading operation. A high drain current flows when the ferroelectric layer is polarized with the second status and low drain current flows when the ferroelectric layer is polarized with the first status. Recorded information can be read by detecting the drain current.

Abstract: A sense circuit includes a sense amplifier and a pull-up resistor circuit disposed on the input side of the sense amplifier. In response to a test selection signal, a read voltage applying circuit applies an external voltage to a selected memory cell and the total resistance of the resistor circuit is switched from a normal resistance to a smaller resistance for testing. Since the input side of the sense amplifier is pulled up through the resistor circuit with the resistance for testing, it is possible to detect the storage state of the selected memory cell under a stricter condition.

Abstract: Nonvolatile memory with simple structure where recorded information can be read without destroy: Voltage is impressed to control gate CG and channel is grounded at writing operation. Ferroelectric layer 32 is polarized in accordance with whether the applied voltage is larger than threshold voltage of the memory device. Control gate voltage V.sub.CC to make channel is little when the ferro-electric layer 32 is polarized with control gate side being positive (polarized with second status). Control gate voltage V.sub.CG to make channel is large when the ferroelectric layer 32 is polarized with control gate side being negative (polarized with first status). The reference voltage V.sub.ref is impressed to the control gate CG at reading operation. Large drain current flows when the ferroelectric layer is polarized with second status and little drain current flows when the ferroelectric layer is polarized with first status. Recorded information can be read by detecting the drain current.

Abstract: A nonvolatile memory having a simple structure where recorded information can be read nondestructively. A voltage is applied between a control gate and a memory gate for writing. A ferroelectric layer is polarized in accordance with the polarization of the applied voltage. A control gate voltage, necessary to form a channel, is small when the ferroelectric layer is polarized with the control gate side negative (polarized with second polarization). The control gate voltage V.sub.cg necessary to form a channel is large when the ferroelectric layer is polarized with the control gate side positive (polarized with first polarization). The reference voltage is applied to the control gate for reading. A large drain current flows when the ferroelectric layer is polarized with the second polarization and a small drain current flows when the ferroelectric layer is polarized with the first polarization. Recorded information can be read by detecting the drain current.

Abstract: In an electrically erasable programmable ROM in which written data contains in a very limited part high-frequency reload data, the memory capacity is reduced in the following new way. An address detecting circuit (12) detects whether or not designated write addresses are within a predetermined range and discriminates the write object data, which is to be high-frequency reload data, if the designated write addresses are within the predetermined range as the result of detection. Then, three sets of identical data (D.sub.7 to D.sub.0) prepared by a data creating circuit (11) are overwritten respectively in three different memory cells (A.sub.0, A.sub.0 ', A.sub.0 "). In data reading, the individual data are read from the respective memory cells, and one of the data decided by a majority logical circuit (15) is outputted as read data.

Abstract: A non-volatile IC memory comprising in addition to a PROM region divided into blocks a RAM region having a capacity corresponding to one of the blocks wherein the entire data stored in the corresponding block in the PROM region designated by an address sent out from the outside is transferred to the RAM region. After data in the corresponding portion in the RAM region designated by the address is rewritten by data sent out from the outside, the data in the RAM region is written back in the corresponding block of the PROM, thereby data is rewritten by a word unit or a bit unit.

Abstract: A PROM IC including sense circuits, each including a sense amplifier. A pull-up resistor circuit whose resistance value is variable is provided on the side of an input of the sense amplifier so that, upon a reception of a test selection signal, the resistance value of the resistor circuit is changed to a value with which a drive condition of current flowing through a selected memory cell becomes severe.