Patents by Inventor Hiromichi Godo

Hiromichi Godo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240143441
    Abstract: To provide an operation method of a semiconductor device in which a variation in arithmetic operation results is reduced. The semiconductor device includes first and second cell arrays and first to fifth circuits. First, third standard data is written from the fourth circuit to the second cell array, and first standard data is written from the first circuit to the first cell array. Then, second standard data is transmitted from the second circuit to the first cell array, a result of a product-sum operation of the first standard data and the second standard data is input from the first cell array to the third circuit, and fourth standard data corresponding to the result of the product-sum operation is transmitted from the third circuit to the second cell array.
    Type: Application
    Filed: October 20, 2023
    Publication date: May 2, 2024
    Inventors: Hidefumi RIKIMARU, Seiko INOUE, Hiromichi GODO, Yoshiyuki KUROKAWA
  • Publication number: 20240134605
    Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a cell array performing a product-sum operation of a first layer and a product-sum operation of a second layer in an artificial neural network, a first circuit from which first data is input to the cell array, and a second circuit to which second data is output from the cell array. The cell array includes a plurality of cells. The cell array includes a first region and a second region. In a first period, the first region is supplied with the t-th (t is a natural number greater than or equal to 2) first data from the first circuit and outputs the t-th second data according to the product-sum operation of the first layer to the second circuit. In the first period, the second region is supplied with the (t+1)-th first data from the first circuit and outputs the (t+1)-th second data according to the product-sum operation of the second layer to the first circuit.
    Type: Application
    Filed: February 24, 2022
    Publication date: April 25, 2024
    Inventors: Yoshiyuki KUROKAWA, Hiromichi GODO, Kazuki TSUDA, Satoru OHSHITA, Hidefumi RIKIMARU
  • Publication number: 20240138167
    Abstract: An electronic device having an eye tracking function is provided. The electronic device includes a display device and an optical system. The display device includes a first light-emitting element, a second light-emitting element, a sensor portion, and a driver circuit portion. The sensor portion includes a light-receiving element. The first light-emitting element has a function of emitting infrared light or visible light. The second light-emitting element has a function of emitting light of a color different from that of light emitted from the first light-emitting element. When the first light-emitting element emits infrared light, the light-receiving element has a function of detecting the infrared light that is emitted from the first light-emitting element and reflected by an eyeball of a user.
    Type: Application
    Filed: February 24, 2022
    Publication date: April 25, 2024
    Inventors: Hiromichi GODO, Yoshiyuki KUROKAWA, Kouhei TOYOTAKA, Kazuki TSUDA, Satoru OHSHITA, Hidefumi RIKIMARU
  • Publication number: 20240113346
    Abstract: A semiconductor device in which a circuit and a battery are efficiently stored is provided. In the semiconductor device, a first transistor, a second transistor, and a secondary battery are provided over one substrate. A channel region of the second transistor includes an oxide semiconductor. The secondary battery includes a solid electrolyte, and can be fabricated by a semiconductor manufacturing process. The substrate may be a semiconductor substrate or a flexible substrate. The secondary battery has a function of being wirelessly charged.
    Type: Application
    Filed: December 8, 2023
    Publication date: April 4, 2024
    Inventors: Junpei MOMO, Kazutaka KURIKI, Hiromichi GODO, Shunpei YAMAZAKI
  • Patent number: 11921919
    Abstract: To provide a novel electronic device. The electronic device includes a housing and a display device. The display device includes a first layer, a second layer, and a third layer. The first layer, the second layer, and the third layer are provided in different layers. The first layer includes a driver circuit and an arithmetic circuit. The second layer includes pixel circuits and a cell array. The third layer includes light-receiving devices and light-emitting devices. The pixel circuits each have a function of controlling light emission of the light-emitting device. The driver circuit has a function of controlling the pixel circuits. The arithmetic circuit has a function of performing arithmetic processing on the basis of first data corresponding to currents output from the light-receiving devices and second data corresponding to a potential held in the cell array.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: March 5, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Hiromichi Godo, Kouhei Toyotaka, Kazuki Tsuda, Satoru Ohshita, Hidefumi Rikimaru
  • Patent number: 11922690
    Abstract: A data processing system, a data processing device, and a data processing method are provided. The data processing system includes a wearable device including a display means and an imaging means and a database that is connected to the wearable device through a network. The database includes at least one of pieces of information on a cooking recipe, a cooking method, and a material. The wearable device detects a first material by the imaging means. The wearable device collects information on the first material from the database. When the first material exists in a specific region in an imaging range of the imaging means, the information on the first material is displayed on the display means. When the first material does not exist in the specific region, the information on the first material is not displayed on the display means.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: March 5, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takuro Kanemura, Taisuke Higashi, Hiroya Hibino, Atsuya Tokinosu, Hiromichi Godo, Satoru Okamoto
  • Publication number: 20240038899
    Abstract: It is an object to provide a highly reliable thin film transistor with stable electric characteristics, which includes an oxide semiconductor film. The channel length of the thin film transistor including the oxide semiconductor film is in the range of 1.5 ?m to 100 ?m inclusive, preferably 3 ?m to 10 ?m inclusive; when the amount of change in threshold voltage is less than or equal to 3 V, preferably less than or equal to 1.5 V in an operation temperature range of room temperature to 180° C. inclusive or ?25° C. to 150° C. inclusive, a semiconductor device with stable electric characteristics can be manufactured. In particular, in a display device which is an embodiment of the semiconductor device, display unevenness due to variation in threshold voltage can be reduced.
    Type: Application
    Filed: October 5, 2023
    Publication date: February 1, 2024
    Inventors: Shunpei YAMAZAKI, Masashi TSUBUKU, Hiromichi GODO
  • Patent number: 11849234
    Abstract: An imaging device with a novel structure is provided. The imaging device includes an imaging region provided with a plurality of pixels. The plurality of pixels included in the imaging region include a first pixel and a second pixel. The imaging device has a function of selecting a first region or a second region. The first region includes the same number of pixels as the second region. The first region includes at least the first and second pixels. The second region includes at least the second pixel. The pixels included in the first region or the second region have a function of outputting imaging signals obtained by the pixels. The imaging device generates first image data by concurrently reading the imaging signals output from the pixels included in the first region and performing arithmetic operation on the signals.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: December 19, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiichi Yoneda, Hiromichi Godo, Yusuke Negoro, Hiroki Inoue, Takahiro Fukutome
  • Patent number: 11848429
    Abstract: A semiconductor device in which a circuit and a battery are efficiently stored is provided. In the semiconductor device, a first transistor, a second transistor, and a secondary battery are provided over one substrate. A channel region of the second transistor includes an oxide semiconductor. The secondary battery includes a solid electrolyte, and can be fabricated by a semiconductor manufacturing process. The substrate may be a semiconductor substrate or a flexible substrate. The secondary battery has a function of being wirelessly charged.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: December 19, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junpei Momo, Kazutaka Kuriki, Hiromichi Godo, Shunpei Yamazaki
  • Publication number: 20230386544
    Abstract: A semiconductor device with low power consumption is provided. The semiconductor device includes a first transistor, a second transistor, and a capacitor. The first transistor includes a first gate and a first back gate, and the second transistor includes a second gate and a second back gate. A gate insulating layer for the first back gate has ferroelectricity. The first transistor has a function of, when being in an off state, retaining a first potential corresponding to first data. The second transistor has a function of making an output current flow between a source and a drain of the second transistor.
    Type: Application
    Filed: September 7, 2021
    Publication date: November 30, 2023
    Inventors: Hiromichi GODO, Yoshiyuki KUROKAWA, Kazuki TSUDA, Satoru OHSHITA
  • Patent number: 11815689
    Abstract: A downsized electronic device with an eye tracking function is provided. The electronic device with an eye tracking function includes a display device, an infrared light source, and an optical system. The display device includes a display element and a light-receiving element; the infrared light source has a function of emitting infrared light; the light-receiving element has a function of detecting the infrared light reflected by an eyeball; and the optical system includes a first optical element positioned on an optical path through which an image from the display element enters the eyeball and a second optical element positioned on an optical path through which the reflected infrared light enters the light-receiving element. The light-receiving element is integrated with the display device and thus, the electronic device can have a reduced size.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: November 14, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisao Ikeda, Yoshiyuki Kurokawa, Hiromichi Godo
  • Patent number: 11817453
    Abstract: A semiconductor device in which a circuit and a power storage element are efficiently placed is provided. The semiconductor device includes a first transistor, a second transistor, and an electric double-layer capacitor. The first transistor, the second transistor, and the electric double-layer capacitor are provided over one substrate. A band gap of a semiconductor constituting a channel region of the second transistor is wider than a band gap of a semiconductor constituting a channel region of the first transistor. The electric double-layer capacitor includes a solid electrolyte.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: November 14, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junpei Momo, Kazutaka Kuriki, Hiromichi Godo
  • Publication number: 20230353163
    Abstract: A novel semiconductor device is provided. An analog signal is converted into a digital signal using a comparison portion comparing two current values, a control portion, and a current output digital-analog conversion portion. The control portion has a function of generating a sign bit showing a magnitude relation between the two current values, a function of converting a difference between the two current values into a digital signal by successive approximation, and a function of outputting the sign bit and the digital signal.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 2, 2023
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takuro KANEMURA, Yoshiyuki KUROKAWA, Hiromichi GODO, Kazuki TSUDA, Satoru OHSHITA, Hidefumi RIKIMARU
  • Publication number: 20230352090
    Abstract: A highly reliable memory device is provided. The memory device includes a first conductor, a second conductor above the first conductor, a third conductor above the second conductor, a fourth conductor above the third conductor, a fifth conductor above the fourth conductor, a sixth conductor above the fifth conductor, a seventh conductor, a first insulator, a second insulator, a first semiconductor, and a second semiconductor. At least third conductor and the fourth conductor have an opening. The first insulator, the first semiconductor, the second insulator, and the second semiconductor are provided in this order on an inner surface of the opening. The seventh conductor is provided between the first semiconductor and the second insulator in a region between the third conductor and the second insulator. The first semiconductor is electrically connected to the second conductor and the fifth conductor. The second semiconductor is electrically connected to the first conductor and the sixth conductor.
    Type: Application
    Filed: December 28, 2020
    Publication date: November 2, 2023
    Inventors: Kazuki TSUDA, Hiromichi GODO, Satoru OHSHITA, Hitoshi KUNITAKE, Satoru OKAMOTO
  • Publication number: 20230284429
    Abstract: Provided is a semiconductor device having a novel structure. A first transistor, a second transistor, a third transistor, and a capacitor are included. The first transistor has a function of retaining a first potential corresponding to first data supplied to a gate of the third transistor through the first transistor when being in an off state. The capacitor has a function of changing the first potential retained in the gate of the third transistor into a second potential in accordance with a change in potential corresponding to second data supplied to one electrode of the capacitor. The second transistor has a function of setting a potential of one of a source and a drain of the third transistor to a potential corresponding to a potential of a gate of the second transistor. The third transistor has a function of supplying output current corresponding to a potential of the gate of the third transistor to the other of the source and the drain of the third transistor.
    Type: Application
    Filed: July 19, 2021
    Publication date: September 7, 2023
    Inventors: Hiromichi GODO, Kazuki TSUDA, Yoshiyuki KUROKAWA, Satoru OHSHITA, Takuro KANEMURA, Hidefumi RIKIMARU
  • Publication number: 20230273637
    Abstract: A control circuit of a secondary battery with a novel structure is provided. The control circuit of a secondary battery includes a first transistor, a first voltage generation circuit generating a first voltage, and a second voltage generation circuit generating a second voltage. The first voltage generation circuit includes a second transistor and a first capacitor. The second voltage generation circuit includes a third transistor and a second capacitor. The difference between the first voltage and the second voltage is set in accordance with the threshold voltage of the first transistor. When the first transistor includes a back gate, a voltage retention circuit having a function of retaining the voltage of the back gate is included. The voltage retention circuit includes a fourth transistor and a third capacitor. The third capacitor includes a ferroelectric layer between a pair of electrodes.
    Type: Application
    Filed: August 25, 2021
    Publication date: August 31, 2023
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki KUROKAWA, Kazuki TSUDA, Hiromichi GODO, Satoru OHSHITA, Takuro KANEMURA, Hidefumi RIKIMARU, Takayuki IKEDA, Yuto YAKUBO, Shunpei YAMAZAKI
  • Patent number: 11715800
    Abstract: An object is to provide a semiconductor device having electrical characteristics such as high withstand voltage, low reverse saturation current, and high on-state current. In particular, an object is to provide a power diode and a rectifier which include non-linear elements. An embodiment of the present invention is a semiconductor device including a first electrode, a gate insulating layer covering the first electrode, an oxide semiconductor layer in contact with the gate insulating layer and overlapping with the first electrode, a pair of second electrodes covering end portions of the oxide semiconductor layer, an insulating layer covering the pair of second electrodes and the oxide semiconductor layer, and a third electrode in contact with the insulating layer and between the pair of second electrodes. The pair of second electrodes are in contact with end surfaces of the oxide semiconductor layer.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: August 1, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiromichi Godo, Satoshi Kobayashi
  • Publication number: 20230065351
    Abstract: A novel semiconductor device is provided. A memory string extends in a Z direction. The memory string achieves high-speed operation by using an oxide semiconductor for a semiconductor layer. The memory string includes a MONOS memory cell. A tunnel layer is provided on a control gate side, and a block layer is provided on a semiconductor side. During erase operation, a hole is injected into a charge accumulation layer from the control gate side.
    Type: Application
    Filed: November 10, 2020
    Publication date: March 2, 2023
    Inventors: Hiromichi GODO, Hitoshi KUNITAKE, Kazuki TSUDA
  • Patent number: 11594176
    Abstract: A semiconductor device with a high driving speed is provided. The semiconductor device includes first to fourth cells, a converter circuit, and first to fourth wirings. The first and second cells make a first current and a second current each corresponding to the product of first data and second data flow in the first wiring and the second wiring, respectively. The third and fourth cells make base currents in the same amount flow in the first and second wirings. The converter circuit outputs, from an output terminal thereof, a voltage corresponding to the differential current between the sum of the first current and the base current flowing in the first wiring and the sum of the second current and the base current flowing in the second wiring.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: February 28, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Yoshiyuki Kurokawa, Kazuki Tsuda, Satoru Ohshita, Hidefumi Rikimaru
  • Publication number: 20230044659
    Abstract: A novel semiconductor device is provided. A memory string, which extends in the Z direction and includes a conductor and an oxide semiconductor, intersects with a plurality of wirings CG extending in the Y direction. The conductor is placed along a center axis of the memory string, and the oxide semiconductor is concentrically placed outside the conductor. The conductor is electrically connected to the oxide semiconductor. An intersection portion of the memory string and the wiring CG functions as a transistor. In addition, the intersection portion functions as a memory cell.
    Type: Application
    Filed: January 6, 2021
    Publication date: February 9, 2023
    Inventors: Hiromichi GODO, Hitoshi KUNITAKE, Kazuki TSUDA