Patents by Inventor Hiromichi Sawaya
Hiromichi Sawaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5561324Abstract: The present invention relates to a semiconductor device which comprises a semiconductor chip mounting section having a through hole, a radiating plate attached to one surface of the semiconductor chip mounting section so as to cover the through hole of the semiconductor chip mounting section, a semiconductor chip mounting plate which is formed within the through hole and mounted on the radiating plate, a surface of the semiconductor chip mounting plate, which is opposite to another surface thereof mounted on the radiating plate, being plated with gold, and the semiconductor chip mounting plate having improved electrical insulation properties and high thermal conductivity, and a semiconductor chip formed within the through hole and attached to the semiconductor chip mounting plate by a conductive adhesive.Type: GrantFiled: March 23, 1995Date of Patent: October 1, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Kozono, Shigeki Sako, Hiromichi Sawaya
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Patent number: 5352632Abstract: A plurality of semiconductor chips are mounted on a plurality of islands formed on a lead frame. Inner lead portions of the lead frame and electrode pads formed on the semiconductor chips are electrically connected to one another via first lead portions formed on a flexible resin tape and the electrode pads formed on the semiconductor chips are connected to one another via second lead portions formed on the flexible resin tape. The flexible resin tape on which the islands and inner lead portions of the lead frame, the plurality of semiconductor chips and the first and second lead portions are formed is sealed into a resin package.Type: GrantFiled: May 17, 1993Date of Patent: October 4, 1994Assignee: Kabushiki Kaisha ToshibaInventor: Hiromichi Sawaya
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Patent number: 5314842Abstract: A resin-sealed type semiconductor device comprises a lead frame having a bed and external leads, a semiconductor element mounted on the bed and having electrodes, a fine metal wire for making an electrical connection between the electrode and the lead frame, a resin layer which seals the semiconductor element, fine metal wire and portion of the lead frame therein and a recess formed at a central portion of one surface side of the resin layer and having a controlled depth, whereby the development of cracks in the resin layer as caused by heat load is prevented.Type: GrantFiled: September 14, 1992Date of Patent: May 24, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Hiromichi Sawaya, Toshio Ishigami
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Patent number: 5245215Abstract: A plurality of semiconductor chips are mounted on a plurality of islands formed on a lead frame. Inner lead portions of the lead frame and electrode pads formed on the semiconductor chips are electrically connected to one another via first lead portions formed on a flexible resin tape and the electrode pads formed on the semiconductor chips are connected to one another via second lead portions formed on the flexible resin tape. The flexible resin tape on which the islands and inner lead portions of the lead frame, the plurality of semiconductor chips and the first and second lead portions are formed is sealed into a resin package.Type: GrantFiled: February 3, 1992Date of Patent: September 14, 1993Assignee: Kabushiki Kaisha ToshibaInventor: Hiromichi Sawaya
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Patent number: 5196992Abstract: A lead of a lead frame cannot be made close to a very small semiconductor chip in view of processing dimensions. If a TAB technique is used to directly connect the semiconductor chip and the lead in order to improve in reliability, a device for forming a bump on an electrode of the chip is required, which increases the cost of investment in equipment. A printed circuit board is formed between the lead and bed and a bonding wire is used to shorten the length of wiring and thus to decrease in cost and improve in reliability. Since an electrode pad of the semiconductor chip, the printed circuit board, and the lead are connected to each other using the TAB techique, the productivity of semiconductor device is increased. Using the TAB technique, no bumps are formed anywhere and the cost of investment in equipment is not so increased.Type: GrantFiled: December 6, 1991Date of Patent: March 23, 1993Assignee: Kabushiki Kaisha ToshibaInventor: Hiromichi Sawaya
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Patent number: 5191511Abstract: A package is formed of a plurality of laminated insulation plates respectively having windows formed in the central portions thereof. Metallized patterns are formed on the surface of at least one of the insulation plates. The semiconductor chip is received in a space defined by the windows of the insulation plates. The semiconductor chip and the metallized patterns are electrically connected to each other via bonding wires. Bumps are arranged as external terminals of the semiconductor chip in a grid form on the surface of one of the insulation plates which lies on the rear surface side of the package. The bumps are electrically connected to the metallized patterns via through holes formed in the insulation plates.Type: GrantFiled: February 4, 1992Date of Patent: March 2, 1993Assignee: Kabushiki Kaisha ToshibaInventor: Hiromichi Sawaya
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Patent number: 5136827Abstract: A wrapping member for holding semiconductor devices comprises a carrier tape and a seal tape. The carrier tape is embossed to form depressed portions, each of which is adapted to receive one semiconductor device. The seal tape is adhered to the carrier tape in a manner to successively cover the depressed portions. A thin metallic film is formed on the surface of at least one of the carrier tape and the seal tape.Type: GrantFiled: October 12, 1990Date of Patent: August 11, 1992Assignee: Kabushiki Kaisha ToshibaInventor: Hiromichi Sawaya
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Patent number: 5124783Abstract: A semiconductor device includes at least one semiconductor chip, an insulating substrate having a predetermined wiring pattern thereon and a conductive island which supports the insulating substrate and the semiconductor chip. The periphery of the insulating substrate is adhered to the conductive island by an insulating adhesive. The semiconductor chip is positioned in a hole formed in the insulating substrate and is adhered to the conductive island by a conductive adhesive.Type: GrantFiled: January 3, 1990Date of Patent: June 23, 1992Assignee: Kabushiki Kaisha ToshibaInventor: Hiromichi Sawaya
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Patent number: 5093713Abstract: A semiconductor device package includes a first semiconductor chip. The first semiconductor chip is mounted on a substrate island region. A lead frame is arranged to serve as an external terminal of the first semiconductor chip, and includes an island region for mounting at least one second semiconductor chip.Type: GrantFiled: May 8, 1991Date of Patent: March 3, 1992Assignee: Kabushiki Kaisha ToshibaInventor: Hiromichi Sawaya
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Patent number: 5083189Abstract: A resin-sealed type integrated circuit device is disclosed which comprises an island constituting a lead frame, and a plurality of hybrid units which, together with the island, are integrally sealed with a resin. The device has the advantages of simplicity of design and reduced size, but without any loss of quality.Type: GrantFiled: April 9, 1990Date of Patent: January 21, 1992Assignee: Kabushiki Kaisha ToshibaInventor: Hiromichi Sawaya
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Patent number: 4963975Abstract: A semiconductor device includes a semiconductor chip, a heat radiation plate having a mounting portion on which the semiconductor chip is mounted, lead terminals connected to the semiconductor chip, a mold resin for sealing the semiconductor chip and parts of the lead terminals in cooperation with the heat radiation plate. The semiconductor device further includes cutput portions for interrupting a stress applied to the semiconductor chip.Type: GrantFiled: January 22, 1990Date of Patent: October 16, 1990Assignee: Kabushiki Kaisha ToshibaInventor: Hiromichi Sawaya
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Patent number: 4951124Abstract: A single in line type semiconductor device is disclosed which has a plurality of lead-in wires extending from a package. In this semiconductor device, a heat sink is embedded in one surface of the package and an appropriate number of lead-in wires are bent on the other surface side of the package, to provide an offset array of the lead-in wires arranged in two rows. A projection is formed on the above appropriate number of lead-in wires on one surface side of the package, such that it extends in a direction perpendicular to that in which the lead-in wires extend. In this semi-conductor device, when the external lead-in wires are inserted into, and joined by means of soldering to a printed circuit board, the package is prevented from being inclined toward the heat sink side by the projection of the external lead-in wire, so that it may be set upright relative to the printed circuit board.Type: GrantFiled: April 28, 1989Date of Patent: August 21, 1990Assignee: Kabushiki Kaisha ToshibaInventor: Hiromichi Sawaya
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Patent number: 4807087Abstract: Disclosed herewith is a single in-line type semiconductor device having external leads drawn out from a package in staggered fashion. According to the single in-line type semiconductor device of this invention, a narrow portion to be fitted in an opening formed in a printed circuit board is provided at each of first and second external leads, with the remaining portion of each external lead constituting a wide portion. The first and second external leads are each provided with a positioning portion defined by the narrow and wide portions. The linear distance between one edge portion of the package and the positioning portion of each first external lead is equal to the linear distance between the edge portion of the package and the positioning portion of each second external lead.Type: GrantFiled: November 18, 1987Date of Patent: February 21, 1989Assignee: Kabushiki Kaisha ToshibaInventor: Hiromichi Sawaya