Abstract: In a transmitting end, positional information indicating positions of data packets to be reproduced in a receiving end among data packets in an inputted bit stream is generated with a plurality of data packets as one unit, and generated one piece of positional information is given to a plurality of data packets, and the data packets with the positional information are transmitted. In a receiving end, reproduction timings are controlled based on the received positional information, and the received data packets are reproduced. As a result, even if a time interval of the data packets to be reproduced in the receiving end in the bit stream inputted into the transmitting end doesn't have a fixed period, the data packets can be reproduced in the receiving end in the same timing as in the transmitting end by only giving one piece of positional information to the plurality of data packets.

Abstract: A RAID controller selecting a plurality of storages forming RAID includes a data input part having a plurality of data input terminals; a control signal input part having a control signal input terminal to which a control signal related to path setting is inputted; a data output part having a plurality of data output terminals; and a path selection part connecting a data input terminal selected from among the plurality of data input terminals with a data output terminal selected from among the plurality of data output terminals based on the control signal when the control signal is inputted to the control signal input terminal.

Abstract: A DMA channel data quantity setting section sets a data transfer quantity of each of a plurality of DMA channels in accordance with a data quantity or a ratio in advance. A channel select control circuit determines whether each DMA channel is active. A data transfer control circuit transfers the data of the DMA channel determined to be active by the channel select control circuit in accordance with the data transfer quantity of each DMA channel set by the DMA channel data quantity setting section. By doing so, a plurality of DMA requests are accepted per bus hold request, and the number of bus management right arbitration procedures and the latency between the channels are decreased.

Abstract: A home gateway apparatus connected to intra-home terminal devices in a home network, has external interfaces to external terminals; internal interfaces to the intra-home terminal devices; a management table memory having management information to be sent and a destination address of the intra-home terminal devices; a management information memory to store the acquired management information; and a management information control unit to send the management information to the external terminal, based on the destination address stored in the management table, after acquiring the management information of the terminal device based on the management information to be sent stored in the management table. The home gateway apparatus can freely select a sending mode of the management information for every intra-home terminal devices, by setting the management table. Therefore, the gateway apparatus having an advanced versatility can be provided.

Abstract: In a transmitting end, positional information indicating positions of data packets to be reproduced in a receiving end among data packets in an inputted bit stream is generated with a plurality of data packets as one unit, and generated one piece of positional information is given to a plurality of data packets, and the data packets with the positional information are transmitted. In a receiving end, reproduction timings are controlled based on the received positional information, and the received data packets are reproduced. As a result, even if a time interval of the data packets to be reproduced in the receiving end in the bit stream inputted into the transmitting end doesn't have a fixed period, the data packets can be reproduced in the receiving end in the same timing as in the transmitting end by only giving one piece of positional information to the plurality of data packets.

Abstract: A DMA channel data quantity setting section sets a data transfer quantity of each of a plurality of DMA channels in accordance with a data quantity or a ratio in advance. A channel select control circuit determines whether each DMA channel is active. A data transfer control circuit transfers the data of the DMA channel determined to be active by the channel select control circuit in accordance with the data transfer quantity of each DMA channel set by the DMA channel data quantity setting section. By doing so, a plurality of DMA requests are accepted per bus hold request, and the number of bus management right arbitration procedures and the latency between the channels are decreased.

Abstract: A home gateway apparatus connected to intra-home terminal devices in a home network, has external interfaces to external terminals; internal interfaces to the intra-home terminal devices; a management table memory having management information to be sent and a destination address of the intra-home terminal devices; a management information memory to store the acquired management information; and a management information control unit to send the management information to the external terminal, based on the destination address stored in the management table, after acquiring the management information of the terminal device based on the management information to be sent stored in the management table. The home gateway apparatus can freely select a sending mode of the management information for every intra-home terminal devices, by setting the management table. Therefore, the gateway apparatus having an advanced versatility can be provided.

Abstract: An image forming apparatus in which a character/line drawing emphasizing section previously stores a correlation between diameter of dots and position of remarked dots to be varied (including movement of a dot position) for each dot pattern in a table, detects a dot pattern matching a dot pattern based on dot image data inputted by a pattern detecting section, and varies and corrects (including movement of a dot position) the diameter of a dot corresponding to a position of a remarked dot in the dot pattern.

Abstract: An image processing apparatus includes a threshold value processing circuit subjecting a correction value with respect to an input image data to a threshold value process and outputting an output image data, a subtracting circuit outputting an error signal based on a difference between the correction value and the output image data, an error filter distributing, as a distributing error data dependent on a value of a diffusion matrix, the error signal to neighborhood pixels of a target pixel within the input image data, and a correction circuit multiplying a coefficient to the input image data or the output image data.

Abstract: A method of achieving halftone representation of image data by using a printer for printing the image data includes the steps of providing a plurality of tone curves which takes into consideration characteristics of the printer, and selecting a tone curve from the plurality of tone curves. The method further includes a step of printing the image data by using the selected tone curve.

Abstract: An image forming apparatus such as an electrophotographic type printer or a facsimile includes a laser diode and a photosensitive drum. A plurality of selective driving circuits are provided for driving the laser diode, and at least one of the driving circuits is selected to form dot images having variable sizes on the photosensitive drum in accordance with a given data supplied by a computer. The driving circuits have different driving currents, and a smaller dot image is formed when a driving circuit providing a lower driving current is selected. Also, delay elements are provided to form a dot image at a delayed timing. The apparatus also has a smoothing function to correct jaggies in a picture.

Abstract: An inverter inverts the polarity of a laser diode driving signal LDS, and a delay circuit delays the laser diode driving signal LDS by the time required for the polarity inversion by the delay circuit. Conduction of first and second switching elements are differentially controlled in accordance with the inversion signal *LDS and a delay signal LDD. When the first switching element is on and the second switching element is off, a driving current Id is supplied to a laser diode so as to emit light. On the other hand, when the first switching element is off and the second switching element is on, a current is supplied to an impedance element, while the driving current Id becomes zero, and the light is extinct.